kai/pounder_test
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speed up pclk again

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This commit is contained in:
Robert Jördens 2019-03-19 21:52:48 +00:00
parent 8fbb1c751b
commit bbe79e3484
2 changed files with 27 additions and 24 deletions
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1
Cargo.toml
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@ -30,6 +30,7 @@ smoltcp = { version = "0.5.0", default-features = false, features = ["proto-ipv4
[features] [features]
semihosting = ["panic-semihosting", "cortex-m-log/semihosting"] semihosting = ["panic-semihosting", "cortex-m-log/semihosting"]
bkpt = [ ]
[build-dependencies] [build-dependencies]
built = "0.3" built = "0.3"

48
src/main.rs
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@ -141,8 +141,8 @@ fn main() -> ! {
rcc.cr.modify(|_, w| w.pll2on().set_bit()); rcc.cr.modify(|_, w| w.pll2on().set_bit());
while rcc.cr.read().pll2rdy().bit_is_clear() {} while rcc.cr.read().pll2rdy().bit_is_clear() {}
// hclk 200 MHz, pclk 50 MHz // hclk 200 MHz, pclk 100 MHz
let dapb = 0b101; let dapb = 0b100;
rcc.d1cfgr.write(|w| unsafe { rcc.d1cfgr.write(|w| unsafe {
w.d1cpre().bits(0) // sys_ck not divided w.d1cpre().bits(0) // sys_ck not divided
.hpre().bits(0b1000) // rcc_hclk3 = sys_d1cpre_ck / 2 .hpre().bits(0b1000) // rcc_hclk3 = sys_d1cpre_ck / 2
@ -267,8 +267,7 @@ fn main() -> ! {
let spi1 = dp.SPI1; let spi1 = dp.SPI1;
spi1.cfg1.modify(|_, w| unsafe { spi1.cfg1.modify(|_, w| unsafe {
// w.mbr().bits(0) // clk/2 w.mbr().bits(0) // clk/2
w.mbr().bits(0) // FIXME
.dsize().bits(16 - 1) .dsize().bits(16 - 1)
.fthvl().bits(1 - 1) // one data .fthvl().bits(1 - 1) // one data
}); });
@ -350,34 +349,37 @@ fn main() -> ! {
.mssi().bits(0) // master SS idle .mssi().bits(0) // master SS idle
}); });
spi2.cr2.modify(|_, w| unsafe { spi2.cr2.modify(|_, w| unsafe {
w.tsize().bits(0) w.tsize().bits(0) // infinite
}); });
spi2.cr1.write(|w| w.spe().set_bit()); spi2.cr1.write(|w| w.spe().set_bit());
// at least one SCK between EOT and CSTART
spi2.cr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 9)) }); spi2.cr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 9)) });
loop { loop {
// cortex_m::interrupt::free(|_cs| { }); #[cfg(feature = "bkpt")]
// spi1.cr1.write(|w| w.cstart().set_bit()); cortex_m::asm::bkpt();
// at least one SCK between EOT and CSTART
spi1.cr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 9)) }); spi1.cr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 9)) });
while spi1.sr.read().eot().bit_is_clear() {} while spi1.sr.read().eot().bit_is_clear() {}
spi1.ifcr.write(|w| w.eotc().set_bit()); spi1.ifcr.write(|w| w.eotc().set_bit());
while spi1.sr.read().rxp().bit_is_set() { while spi1.sr.read().rxp().bit_is_clear() {}
let a = spi1.rxdr.read().rxdr().bits() as i16; let a = spi1.rxdr.read().rxdr().bits() as i16;
let d = (a as u16) ^ 0x8000; let d = (a as u16) ^ 0x8000;
// while spi2.sr.read().txp().bit_is_clear() {} while spi2.sr.read().txp().bit_is_clear() {}
// spi2.txdr.write(|w| unsafe { w.bits(d as u32) }); let txdr = &spi2.txdr as *const _ as *mut u16;
unsafe { ptr::write_volatile(&spi2.txdr as *const _ as *mut u16, d) }; unsafe { ptr::write_volatile(txdr, d) };
// write(|w| unsafe { w.bits(d as u32) }); while spi2.sr.read().txc().bit_is_clear() {}
// while spi2.sr.read().txc().bit_is_clear() {}
// while spi2.sr.read().eot().bit_is_clear() {} #[cfg(feature = "bkpt")]
// spi2.ifcr.write(|w| w.eotc().set_bit()); cortex_m::asm::bkpt();
info!("dac adc {:#x} cr1 {:#x} sr {:#x} cfg1 {:#x} cr2 {:#x}",
a, info!("dac adc {:#x} cr1 {:#x} sr {:#x} cfg1 {:#x} cr2 {:#x}",
spi2.cr1.read().bits(), spi2.sr.read().bits(), a,
spi2.cfg1.read().bits(), spi2.cr2.read().bits(), spi2.cr1.read().bits(), spi2.sr.read().bits(),
); spi2.cfg1.read().bits(), spi2.cr2.read().bits(),
} );
// cortex_m::asm::wfi(); // cortex_m::asm::wfi();
} }
} }