From b7100f2b146059d0184ae184eff6a9ab68baca69 Mon Sep 17 00:00:00 2001
From: Ryan Summers <ryan.summers@vertigo-designs.com>
Date: Thu, 11 Jun 2020 19:00:37 +0200
Subject: [PATCH] Correcting issues at high optimization levels

---
 Cargo.toml        |  3 ++-
 ad9959/src/lib.rs | 11 +++++------
 stm32h7xx-hal     |  2 +-
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/Cargo.toml b/Cargo.toml
index ec83f63..0f43a74 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -9,9 +9,10 @@ members = [
 [profile.dev]
 codegen-units = 1
 incremental = false
-opt-level = 1
+opt-level = 3
 
 [profile.release]
+opt-level = 3
 debug = true
 lto = true
 codegen-units = 1
diff --git a/ad9959/src/lib.rs b/ad9959/src/lib.rs
index 13ea7cf..558772d 100644
--- a/ad9959/src/lib.rs
+++ b/ad9959/src/lib.rs
@@ -152,12 +152,11 @@ where
         ad9959.interface.configure_mode(desired_mode).map_err(|_| Error::Interface)?;
 
         // Read back the CSR to ensure it specifies the mode correctly.
-        // TODO: This is disabled until QSPI readback issues have been resolved.
-        //let mut updated_csr: [u8; 1] = [0];
-        //ad9959.interface.read(Register::CSR as u8, &mut updated_csr).map_err(|_| Error::Interface)?;
-        //if updated_csr[0] != csr[0] {
-        //    return Err(Error::Check);
-        //}
+        let mut updated_csr: [u8; 1] = [0];
+        ad9959.interface.read(Register::CSR as u8, &mut updated_csr).map_err(|_| Error::Interface)?;
+        if updated_csr[0] != csr[0] {
+            return Err(Error::Check);
+        }
 
         // Set the clock frequency to configure the device as necessary.
         ad9959.configure_system_clock(clock_frequency, multiplier)?;
diff --git a/stm32h7xx-hal b/stm32h7xx-hal
index d79cb00..40ad468 160000
--- a/stm32h7xx-hal
+++ b/stm32h7xx-hal
@@ -1 +1 @@
-Subproject commit d79cb0015a6f0cbb819907efe3a817f7dce14bab
+Subproject commit 40ad4687e8473e329aea4b61551d107f3dfca567