diff --git a/Cargo.lock b/Cargo.lock index 9f1bb5d..f247a6c 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -501,7 +501,7 @@ dependencies = [ [[package]] name = "stm32h7xx-hal" version = "0.8.0" -source = "git+https://github.com/quartiq/stm32h7xx-hal?branch=feature/stabilizer-dma#5fbbfa9352f720994c210e5c21601f3acf9dc40c" +source = "git+https://github.com/quartiq/stm32h7xx-hal?branch=feature/dma-rtic-example#d8cb6fa5099282665f5e5068a9dcdc9ebaa63240" dependencies = [ "bare-metal 1.0.0", "cast", diff --git a/Cargo.toml b/Cargo.toml index 04bd4e5..049e61c 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -55,7 +55,7 @@ path = "ad9959" [dependencies.stm32h7xx-hal] features = ["stm32h743v", "rt", "unproven", "ethernet", "quadspi"] git = "https://github.com/quartiq/stm32h7xx-hal" -branch = "feature/stabilizer-dma" +branch = "feature/dma-rtic-example" [features] semihosting = ["panic-semihosting", "cortex-m-log/semihosting"] @@ -65,7 +65,7 @@ nightly = ["cortex-m/inline-asm"] [profile.dev] codegen-units = 1 incremental = false -opt-level = 1 +opt-level = 3 [profile.release] opt-level = 3 diff --git a/src/adc.rs b/src/adc.rs index cb15c27..039a7c3 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -1,13 +1,36 @@ +///! Stabilizer ADC management interface +///! +///! The Stabilizer ADCs utilize a DMA channel to trigger sampling. The SPI streams are configured +///! for full-duplex operation, but only RX is connected to physical pins. A timer channel is +///! configured to generate a DMA write into the SPI TXFIFO, which initiates a SPI transfer and +///! results in an ADC sample read for both channels. +///! +///! In order to read multiple samples without interrupting the CPU, a separate DMA transfer is +///! configured to read from each of the ADC SPI RX FIFOs. Due to the design of the SPI peripheral, +///! these DMA transfers stall when no data is available in the FIFO. Thus, the DMA transfer only +///! completes after all samples have been read. When this occurs, a CPU interrupt is generated so +///! that software can process the acquired samples from both ADCs. Only one of the ADC DMA streams +///! is configured to generate an interrupt to handle both transfers, so it is necessary to ensure +///! both transfers are completed before reading the data. This is usually not significant for +///! busy-waiting because the transfers should complete at approximately the same time. use super::{ - hal, DMAReq, DmaConfig, MemoryToPeripheral, PeripheralToMemory, Priority, - Stream, TargetAddress, Transfer, + hal, DMAReq, DmaConfig, MemoryToPeripheral, PeripheralToMemory, Priority, TargetAddress, + Transfer, }; +// The desired ADC input buffer size. This is use configurable. const INPUT_BUFFER_SIZE: usize = 1; +// The following data is written by the timer ADC sample trigger into each of the SPI TXFIFOs. Note +// that because the SPI MOSI line is not connected, this data is dont-care. Data in AXI SRAM is not +// initialized on boot, so the contents are random. #[link_section = ".axisram.buffers"] static mut SPI_START: [u16; 1] = [0x00]; +// The following global buffers are used for the ADC sample DMA transfers. Two buffers are used for +// each transfer in a ping-pong buffer configuration (one is being acquired while the other is being +// processed). Note that the contents of AXI SRAM is uninitialized, so the buffer contents on +// startup are undefined. #[link_section = ".axisram.buffers"] static mut ADC0_BUF0: [u16; INPUT_BUFFER_SIZE] = [0; INPUT_BUFFER_SIZE]; @@ -20,8 +43,9 @@ static mut ADC1_BUF0: [u16; INPUT_BUFFER_SIZE] = [0; INPUT_BUFFER_SIZE]; #[link_section = ".axisram.buffers"] static mut ADC1_BUF1: [u16; INPUT_BUFFER_SIZE] = [0; INPUT_BUFFER_SIZE]; +/// SPI2 is used as a ZST (zero-sized type) for indicating a DMA transfer into the SPI2 TX FIFO +/// whenever the tim2 update dma request occurs. struct SPI2 {} - impl SPI2 { pub fn new() -> Self { Self {} @@ -29,18 +53,23 @@ impl SPI2 { } unsafe impl TargetAddress for SPI2 { + /// SPI2 is configured to operate using 16-bit transfer words. type MemSize = u16; - const REQUEST_LINE: Option = Some(DMAReq::TIM2_UP as u8); + /// SPI2 DMA requests are generated whenever TIM2 CH1 comparison occurs. + const REQUEST_LINE: Option = Some(DMAReq::TIM2_CH1 as u8); + /// Whenever the DMA request occurs, it should write into SPI2's TX FIFO to start a DMA + /// transfer. fn address(&self) -> u32 { let regs = unsafe { &*hal::stm32::SPI2::ptr() }; ®s.txdr as *const _ as u32 } } +/// SPI3 is used as a ZST (zero-sized type) for indicating a DMA transfer into the SPI3 TX FIFO +/// whenever the tim2 update dma request occurs. struct SPI3 {} - impl SPI3 { pub fn new() -> Self { Self {} @@ -48,26 +77,37 @@ impl SPI3 { } unsafe impl TargetAddress for SPI3 { + /// SPI3 is configured to operate using 16-bit transfer words. type MemSize = u16; - const REQUEST_LINE: Option = Some(DMAReq::TIM2_UP as u8); + /// SPI3 DMA requests are generated whenever TIM2 CH2 comparison occurs. + const REQUEST_LINE: Option = Some(DMAReq::TIM2_CH2 as u8); + /// Whenever the DMA request occurs, it should write into SPI3's TX FIFO to start a DMA + /// transfer. fn address(&self) -> u32 { let regs = unsafe { &*hal::stm32::SPI3::ptr() }; ®s.txdr as *const _ as u32 } } +/// Represents both ADC input channels. pub struct AdcInputs { adc0: Adc0Input, adc1: Adc1Input, } impl AdcInputs { + /// Construct the ADC inputs. pub fn new(adc0: Adc0Input, adc1: Adc1Input) -> Self { Self { adc0, adc1 } } + /// Interrupt handler to handle when the sample collection DMA transfer completes. + /// + /// # Returns + /// (adc0, adc1) where adcN is a reference to the collected ADC samples. Two array references + /// are returned - one for each ADC sample stream. pub fn transfer_complete_handler( &mut self, ) -> (&[u16; INPUT_BUFFER_SIZE], &[u16; INPUT_BUFFER_SIZE]) { @@ -77,6 +117,7 @@ impl AdcInputs { } } +/// Represents data associated with ADC0. pub struct Adc0Input { next_buffer: Option<&'static mut [u16; INPUT_BUFFER_SIZE]>, transfer: Transfer< @@ -85,72 +126,113 @@ pub struct Adc0Input { PeripheralToMemory, &'static mut [u16; INPUT_BUFFER_SIZE], >, + _trigger_transfer: Transfer< + hal::dma::dma::Stream0, + SPI2, + MemoryToPeripheral, + &'static mut [u16; 1], + >, } impl Adc0Input { + /// Construct the ADC0 input channel. + /// + /// # Args + /// * `spi` - The SPI interface used to communicate with the ADC. + /// * `trigger_stream` - The DMA stream used to trigger each ADC transfer by writing a word into + /// the SPI TX FIFO. + /// * `data_stream` - The DMA stream used to read samples received over SPI into a data buffer. pub fn new( spi: hal::spi::Spi, trigger_stream: hal::dma::dma::Stream0, data_stream: hal::dma::dma::Stream1, ) -> Self { + // The trigger stream constantly writes to the TX FIFO using a static word (dont-care + // contents). Thus, neither the memory or peripheral address ever change. This is run in + // circular mode to be completed at every DMA request. let trigger_config = DmaConfig::default() .memory_increment(false) .peripheral_increment(false) .priority(Priority::High) .circular_buffer(true); + // Construct the trigger stream to write from memory to the peripheral. let mut trigger_transfer: Transfer<_, _, MemoryToPeripheral, _> = Transfer::init( trigger_stream, - &SPI2::new(), + SPI2::new(), unsafe { &mut SPI_START }, None, trigger_config, ); + // The data stream constantly reads from the SPI RX FIFO into a RAM buffer. The peripheral + // stalls reads of the SPI RX FIFO until data is available, so the DMA transfer completes + // after the requested number of samples have been collected. Note that only ADC1's data + // stream is used to trigger a transfer completion interrupt. let data_config = DmaConfig::default() .memory_increment(true) .priority(Priority::VeryHigh) .peripheral_increment(false); + // A SPI peripheral error interrupt is used to determine if the RX FIFO overflows. This + // indicates that samples were dropped due to excessive processing time in the main + // application (e.g. a second DMA transfer completes before the first was done with + // processing). This is used as a flow control indicator to guarantee that no ADC samples + // are lost. let mut spi = spi.disable(); spi.listen(hal::spi::Event::Error); + // The data transfer is always a transfer of data from the peripheral to a RAM buffer. let mut data_transfer: Transfer<_, _, PeripheralToMemory, _> = Transfer::init( data_stream, - &spi, + spi, unsafe { &mut ADC0_BUF0 }, None, data_config, ); - spi.enable_dma_rx(); - spi.enable_dma_tx(); + data_transfer.start(|spi| { + // Allow the SPI FIFOs to operate using only DMA data channels. + spi.enable_dma_rx(); + spi.enable_dma_tx(); - let spi = spi.enable(); - spi.inner().cr1.modify(|_, w| w.cstart().started()); + // Enable SPI and start it in infinite transaction mode. + spi.inner().cr1.modify(|_, w| w.spe().set_bit()); + spi.inner().cr1.modify(|_, w| w.cstart().started()); + }); - data_transfer.start(); - trigger_transfer.start(); + trigger_transfer.start(|_| {}); Self { next_buffer: unsafe { Some(&mut ADC0_BUF1) }, transfer: data_transfer, + _trigger_transfer: trigger_transfer, } } + /// Handle a transfer completion. + /// + /// # Returns + /// A reference to the underlying buffer that has been filled with ADC samples. pub fn transfer_complete_handler(&mut self) -> &[u16; INPUT_BUFFER_SIZE] { let next_buffer = self.next_buffer.take().unwrap(); - while hal::dma::dma::Stream1::::is_enabled() {} + + // Wait for the transfer to fully complete before continuing. + while self.transfer.get_transfer_complete_flag() == false {} + + // Start the next transfer. self.transfer.clear_interrupts(); let (prev_buffer, _) = self.transfer.next_transfer(next_buffer).unwrap(); + self.next_buffer.replace(prev_buffer); self.next_buffer.as_ref().unwrap() } } +/// Represents the data input stream from ADC1 pub struct Adc1Input { next_buffer: Option<&'static mut [u16; INPUT_BUFFER_SIZE]>, transfer: Transfer< @@ -159,68 +241,107 @@ pub struct Adc1Input { PeripheralToMemory, &'static mut [u16; INPUT_BUFFER_SIZE], >, + _trigger_transfer: Transfer< + hal::dma::dma::Stream2, + SPI3, + MemoryToPeripheral, + &'static mut [u16; 1], + >, } impl Adc1Input { + /// Construct a new ADC1 input data stream. + /// + /// # Args + /// * `spi` - The SPI interface connected to ADC1. + /// * `trigger_stream` - The DMA stream used to trigger ADC conversions on the SPI interface. + /// * `data_stream` - The DMA stream used to read ADC samples from the SPI RX FIFO. pub fn new( spi: hal::spi::Spi, trigger_stream: hal::dma::dma::Stream2, data_stream: hal::dma::dma::Stream3, ) -> Self { + // The trigger stream constantly writes to the TX FIFO using a static word (dont-care + // contents). Thus, neither the memory or peripheral address ever change. This is run in + // circular mode to be completed at every DMA request. let trigger_config = DmaConfig::default() .memory_increment(false) .peripheral_increment(false) .priority(Priority::High) .circular_buffer(true); + // Construct the trigger stream to write from memory to the peripheral. let mut trigger_transfer: Transfer<_, _, MemoryToPeripheral, _> = Transfer::init( trigger_stream, - &SPI3::new(), + SPI3::new(), unsafe { &mut SPI_START }, None, trigger_config, ); + // The data stream constantly reads from the SPI RX FIFO into a RAM buffer. The peripheral + // stalls reads of the SPI RX FIFO until data is available, so the DMA transfer completes + // after the requested number of samples have been collected. Note that only ADC1's data + // stream is used to trigger a transfer completion interrupt. let data_config = DmaConfig::default() .memory_increment(true) .transfer_complete_interrupt(true) .priority(Priority::VeryHigh) .peripheral_increment(false); + // A SPI peripheral error interrupt is used to determine if the RX FIFO overflows. This + // indicates that samples were dropped due to excessive processing time in the main + // application (e.g. a second DMA transfer completes before the first was done with + // processing). This is used as a flow control indicator to guarantee that no ADC samples + // are lost. let mut spi = spi.disable(); spi.listen(hal::spi::Event::Error); + // The data transfer is always a transfer of data from the peripheral to a RAM buffer. let mut data_transfer: Transfer<_, _, PeripheralToMemory, _> = Transfer::init( data_stream, - &spi, + spi, unsafe { &mut ADC1_BUF0 }, None, data_config, ); - spi.enable_dma_rx(); - spi.enable_dma_tx(); + data_transfer.start(|spi| { + // Allow the SPI FIFOs to operate using only DMA data channels. + spi.enable_dma_rx(); + spi.enable_dma_tx(); - let spi = spi.enable(); - spi.inner().cr1.modify(|_, w| w.cstart().started()); + // Enable SPI and start it in infinite transaction mode. + spi.inner().cr1.modify(|_, w| w.spe().set_bit()); + spi.inner().cr1.modify(|_, w| w.cstart().started()); + }); - data_transfer.start(); - trigger_transfer.start(); + trigger_transfer.start(|_| {}); Self { next_buffer: unsafe { Some(&mut ADC1_BUF1) }, transfer: data_transfer, + _trigger_transfer: trigger_transfer, } } + /// Handle a transfer completion. + /// + /// # Returns + /// A reference to the underlying buffer that has been filled with ADC samples. pub fn transfer_complete_handler(&mut self) -> &[u16; INPUT_BUFFER_SIZE] { let next_buffer = self.next_buffer.take().unwrap(); - while hal::dma::dma::Stream3::::is_enabled() {} + + // Wait for the transfer to fully complete before continuing. + while self.transfer.get_transfer_complete_flag() == false {} + + // Start the next transfer. self.transfer.clear_interrupts(); let (prev_buffer, _) = self.transfer.next_transfer(next_buffer).unwrap(); + self.next_buffer.replace(prev_buffer); self.next_buffer.as_ref().unwrap() } diff --git a/src/main.rs b/src/main.rs index 3a0b00e..b7cf7db 100644 --- a/src/main.rs +++ b/src/main.rs @@ -1,6 +1,4 @@ #![deny(warnings)] -// Deprecation warnings are temporarily allowed as the HAL DMA goes through updates. -#![allow(deprecated)] #![allow(clippy::missing_safety_doc)] #![no_std] #![no_main] @@ -41,7 +39,7 @@ use hal::{ dma::{ config::Priority, dma::{DMAReq, DmaConfig}, - traits::{Stream, TargetAddress}, + traits::TargetAddress, MemoryToPeripheral, PeripheralToMemory, Transfer, }, ethernet::{self, PHY}, @@ -706,8 +704,14 @@ const APP: () = { &ccdr.clocks, ); { + // Listen to the CH1 and CH2 comparison events. These channels should have a value of + // zero loaded into them, so the event should occur whenever the timer overflows. Note + // that we use channels instead of timer updates because each SPI DMA transfer needs a + // unique request line. let t2_regs = unsafe { &*hal::stm32::TIM2::ptr() }; - t2_regs.dier.modify(|_, w| w.ude().set_bit()); + t2_regs + .dier + .modify(|_, w| w.cc1de().set_bit().cc2de().set_bit()); } init::LateResources {