Merge pull request #195 from vertigo-designs/feature/digital-input-stamp
Feature/digital input stampmaster
Ryan Summers
GitHub
commit
a2fb4630b8
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@ -874,7 +874,7 @@ dependencies = [
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[[package]]
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name = "stm32h7xx-hal"
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version = "0.8.0"
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source = "git+https://github.com/stm32-rs/stm32h7xx-hal?branch=dma#0bfeeca4ce120c1b7c6d140a7da73a4372b874d8"
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source = "git+https://github.com/stm32-rs/stm32h7xx-hal?branch=dma#25ee0f3a9ae27d1fd6bb390d6045aa312f29f096"
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dependencies = [
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"bare-metal 1.0.0",
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"cast",
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14
src/adc.rs
14
src/adc.rs
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@ -14,8 +14,8 @@
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///! both transfers are completed before reading the data. This is usually not significant for
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///! busy-waiting because the transfers should complete at approximately the same time.
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use super::{
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hal, sampling_timer, DMAReq, DmaConfig, MemoryToPeripheral,
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PeripheralToMemory, Priority, TargetAddress, Transfer, SAMPLE_BUFFER_SIZE,
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hal, timers, DMAReq, DmaConfig, MemoryToPeripheral, PeripheralToMemory,
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Priority, TargetAddress, Transfer, SAMPLE_BUFFER_SIZE,
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};
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// The following data is written by the timer ADC sample trigger into each of the SPI TXFIFOs. Note
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@ -38,12 +38,10 @@ macro_rules! adc_input {
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/// $spi is used as a type for indicating a DMA transfer into the SPI TX FIFO
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/// whenever the tim2 update dma request occurs.
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struct $spi {
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_channel: sampling_timer::tim2::$trigger_channel,
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_channel: timers::tim2::$trigger_channel,
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}
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impl $spi {
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pub fn new(
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_channel: sampling_timer::tim2::$trigger_channel,
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) -> Self {
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pub fn new(_channel: timers::tim2::$trigger_channel) -> Self {
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Self { _channel }
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}
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}
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@ -100,7 +98,7 @@ macro_rules! adc_input {
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hal::stm32::DMA1,
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>,
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data_stream: hal::dma::dma::$data_stream<hal::stm32::DMA1>,
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trigger_channel: sampling_timer::tim2::$trigger_channel,
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trigger_channel: timers::tim2::$trigger_channel,
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) -> Self {
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// Generate DMA events when an output compare of the timer hitting zero (timer roll over)
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// occurs.
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@ -195,7 +193,7 @@ macro_rules! adc_input {
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// Start the next transfer.
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self.transfer.clear_interrupts();
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let (prev_buffer, _) =
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let (prev_buffer, _, _) =
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self.transfer.next_transfer(next_buffer).unwrap();
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self.next_buffer.replace(prev_buffer); // .unwrap_none() https://github.com/rust-lang/rust/issues/62633
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10
src/dac.rs
10
src/dac.rs
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@ -4,7 +4,7 @@
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///! configured to generate a DMA write into the SPI TXFIFO, which initiates a SPI transfer and
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///! results in DAC update for both channels.
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use super::{
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hal, sampling_timer, DMAReq, DmaConfig, MemoryToPeripheral, TargetAddress,
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hal, timers, DMAReq, DmaConfig, MemoryToPeripheral, TargetAddress,
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Transfer, SAMPLE_BUFFER_SIZE,
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};
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@ -22,12 +22,12 @@ macro_rules! dac_output {
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/// $spi is used as a type for indicating a DMA transfer into the SPI TX FIFO
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struct $spi {
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spi: hal::spi::Spi<hal::stm32::$spi, hal::spi::Disabled, u16>,
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_channel: sampling_timer::tim2::$trigger_channel,
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_channel: timers::tim2::$trigger_channel,
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}
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impl $spi {
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pub fn new(
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_channel: sampling_timer::tim2::$trigger_channel,
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_channel: timers::tim2::$trigger_channel,
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spi: hal::spi::Spi<hal::stm32::$spi, hal::spi::Disabled, u16>,
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) -> Self {
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Self { _channel, spi }
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@ -73,7 +73,7 @@ macro_rules! dac_output {
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pub fn new(
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spi: hal::spi::Spi<hal::stm32::$spi, hal::spi::Enabled, u16>,
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stream: hal::dma::dma::$data_stream<hal::stm32::DMA1>,
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trigger_channel: sampling_timer::tim2::$trigger_channel,
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trigger_channel: timers::tim2::$trigger_channel,
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) -> Self {
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// Generate DMA events when an output compare of the timer hitting zero (timer roll over)
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// occurs.
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@ -143,7 +143,7 @@ macro_rules! dac_output {
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// Start the next transfer.
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self.transfer.clear_interrupts();
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let (prev_buffer, _) =
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let (prev_buffer, _, _) =
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self.transfer.next_transfer(next_buffer).unwrap();
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// .unwrap_none() https://github.com/rust-lang/rust/issues/62633
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@ -1,6 +1,26 @@
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use super::hal::time::MegaHertz;
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/// The ADC setup time is the number of seconds after the CSn line goes low before the serial clock
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/// may begin. This is used for performing the internal ADC conversion.
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pub const ADC_SETUP_TIME: f32 = 220e-9;
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/// The maximum DAC/ADC serial clock line frequency. This is a hardware limit.
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pub const ADC_DAC_SCK_MHZ_MAX: u32 = 50;
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pub const ADC_DAC_SCK_MAX: MegaHertz = MegaHertz(50);
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/// The optimal counting frequency of the hardware timers used for timestamping and sampling.
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pub const TIMER_FREQUENCY: MegaHertz = MegaHertz(100);
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/// The QSPI frequency for communicating with the pounder DDS.
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pub const POUNDER_QSPI_FREQUENCY: MegaHertz = MegaHertz(40);
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/// The delay after initiating a QSPI transfer before asserting the IO_Update for the pounder DDS.
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// Pounder Profile writes are always 16 bytes, with 2 cycles required per byte, coming out to a
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// total of 32 QSPI clock cycles. The QSPI is configured for 40MHz, so this comes out to an offset
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// of 800nS. We use 900ns to be safe.
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pub const POUNDER_IO_UPDATE_DELAY: f32 = 900_e-9;
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/// The duration to assert IO_Update for the pounder DDS.
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// IO_Update should be latched for 4 SYNC_CLK cycles after the QSPI profile write. With pounder
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// SYNC_CLK running at 100MHz (1/4 of the pounder reference clock of 400MHz), this corresponds to
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// 40ns. To accomodate rounding errors, we use 50ns instead.
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pub const POUNDER_IO_UPDATE_DURATION: f32 = 50_e-9;
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@ -0,0 +1,109 @@
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///! Digital Input 0 (DI0) reference clock timestamper
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///!
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///! This module provides a means of timestamping the rising edges of an external reference clock on
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///! the DI0 with a timer value from TIM5.
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///!
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///! # Design
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///! An input capture channel is configured on DI0 and fed into TIM5's capture channel 4. TIM5 is
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///! then run in a free-running mode with a configured tick rate (PSC) and maximum count value
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///! (ARR). Whenever an edge on DI0 triggers, the current TIM5 counter value is captured and
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///! recorded as a timestamp. This timestamp can be either directly read from the timer channel or
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///! can be collected asynchronously via DMA collection.
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///!
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///! To prevent silently discarding timestamps, the TIM5 input capture over-capture flag is
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///! continually checked. Any over-capture event (which indicates an overwritten timestamp) then
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///! triggers a panic to indicate the dropped timestamp so that design parameters can be adjusted.
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///!
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///! # Tradeoffs
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///! It appears that DMA transfers can take a significant amount of time to disable (400ns) if they
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///! are being prematurely stopped (such is the case here). As such, for a sample batch size of 1,
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///! this can take up a significant amount of the total available processing time for the samples.
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///! This module checks for any captured timestamps from the timer capture channel manually. In
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///! this mode, the maximum input clock frequency supported is dependant on the sampling rate and
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///! batch size.
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///!
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///! This module only supports DI0 for timestamping due to trigger constraints on the DIx pins. If
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///! timestamping is desired in DI1, a separate timer + capture channel will be necessary.
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use super::{hal, timers, ADC_SAMPLE_TICKS, SAMPLE_BUFFER_SIZE};
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/// Calculate the period of the digital input timestampe timer.
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///
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/// # Note
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/// The period returned will be 1 less than the required period in timer ticks. The value returned
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/// can be immediately programmed into a hardware timer period register.
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///
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/// The period is calcualted to be some power-of-two multiple of the batch size, such that N batches
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/// will occur between each timestamp timer overflow.
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///
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/// # Returns
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/// A 32-bit value that can be programmed into a hardware timer period register.
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pub fn calculate_timestamp_timer_period() -> u32 {
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// Calculate how long a single batch requires in timer ticks.
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let batch_duration_ticks: u64 =
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SAMPLE_BUFFER_SIZE as u64 * ADC_SAMPLE_TICKS as u64;
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// Calculate the largest power-of-two that is less than or equal to
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// `batches_per_overflow`. This is completed by eliminating the least significant
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// bits of the value until only the msb remains, which is always a power of two.
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let batches_per_overflow: u64 =
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(1u64 + u32::MAX as u64) / batch_duration_ticks;
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let mut j = batches_per_overflow;
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while (j & (j - 1)) != 0 {
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j = j & (j - 1);
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}
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// Once the number of batches per timestamp overflow is calculated, we can figure out the final
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// period of the timestamp timer. The period is always 1 larger than the value configured in the
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// register.
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let period: u64 = batch_duration_ticks * j - 1u64;
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assert!(period <= u32::MAX as u64);
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period as u32
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}
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/// The timestamper for DI0 reference clock inputs.
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pub struct InputStamper {
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_di0_trigger: hal::gpio::gpioa::PA3<hal::gpio::Alternate<hal::gpio::AF2>>,
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capture_channel: timers::tim5::Channel4InputCapture,
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}
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impl InputStamper {
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/// Construct the DI0 input timestamper.
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///
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/// # Args
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/// * `trigger` - The capture trigger input pin.
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/// * `timer_channel - The timer channel used for capturing timestamps.
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pub fn new(
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trigger: hal::gpio::gpioa::PA3<hal::gpio::Alternate<hal::gpio::AF2>>,
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timer_channel: timers::tim5::Channel4,
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) -> Self {
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// Utilize the TIM5 CH4 as an input capture channel - use TI4 (the DI0 input trigger) as the
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// capture source.
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let input_capture =
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timer_channel.into_input_capture(timers::tim5::CC4S_A::TI4);
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Self {
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capture_channel: input_capture,
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_di0_trigger: trigger,
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}
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}
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/// Start to capture timestamps on DI0.
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pub fn start(&mut self) {
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self.capture_channel.enable();
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}
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/// Get the latest timestamp that has occurred.
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///
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/// # Note
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/// This function must be called sufficiently often. If an over-capture event occurs, this
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/// function will panic, as this indicates a timestamp was inadvertently dropped.
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///
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/// To prevent timestamp loss, the batch size and sampling rate must be adjusted such that at
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/// most one timestamp will occur in each data processing cycle.
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pub fn latest_timestamp(&mut self) -> Option<u32> {
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self.capture_channel
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.latest_capture()
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.expect("DI0 timestamp overrun")
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}
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}
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110
src/main.rs
110
src/main.rs
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@ -54,8 +54,10 @@ use smoltcp::wire::Ipv4Address;
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use heapless::{consts::*, String};
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// The desired sampling frequency of the ADCs.
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const SAMPLE_FREQUENCY_KHZ: u32 = 500;
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// The number of ticks in the ADC sampling timer. The timer runs at 100MHz, so the step size is
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// equal to 10ns per tick.
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// Currently, the sample rate is equal to: Fsample = 100/256 MHz = 390.625 KHz
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const ADC_SAMPLE_TICKS: u32 = 256;
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// The desired ADC sample processing buffer size.
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const SAMPLE_BUFFER_SIZE: usize = 1;
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@ -70,11 +72,12 @@ mod adc;
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mod afe;
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mod dac;
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mod design_parameters;
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mod digital_input_stamper;
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mod eeprom;
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mod hrtimer;
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mod pounder;
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mod sampling_timer;
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mod server;
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mod timers;
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use adc::{Adc0Input, Adc1Input};
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use dac::{Dac0Output, Dac1Output};
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@ -196,9 +199,9 @@ macro_rules! route_request {
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const APP: () = {
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struct Resources {
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afes: (AFE0, AFE1),
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adcs: (Adc0Input, Adc1Input),
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dacs: (Dac0Output, Dac1Output),
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input_stamper: digital_input_stamper::InputStamper,
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eeprom_i2c: hal::i2c::I2c<hal::stm32::I2C2>,
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@ -281,15 +284,50 @@ const APP: () = {
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hal::dma::dma::StreamsTuple::new(dp.DMA1, ccdr.peripheral.DMA1);
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// Configure timer 2 to trigger conversions for the ADC
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let timer2 = dp.TIM2.timer(
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SAMPLE_FREQUENCY_KHZ.khz(),
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ccdr.peripheral.TIM2,
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&ccdr.clocks,
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);
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let mut sampling_timer = {
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// The timer frequency is manually adjusted below, so the 1KHz setting here is a
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// dont-care.
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let mut timer2 =
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dp.TIM2.timer(1.khz(), ccdr.peripheral.TIM2, &ccdr.clocks);
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// Configure the timer to count at the designed tick rate. We will manually set the
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// period below.
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timer2.pause();
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timer2.set_tick_freq(design_parameters::TIMER_FREQUENCY);
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let mut sampling_timer = timers::SamplingTimer::new(timer2);
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sampling_timer.set_period_ticks(ADC_SAMPLE_TICKS - 1);
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sampling_timer
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};
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let mut sampling_timer = sampling_timer::SamplingTimer::new(timer2);
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let sampling_timer_channels = sampling_timer.channels();
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let mut timestamp_timer = {
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// The timer frequency is manually adjusted below, so the 1KHz setting here is a
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// dont-care.
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let mut timer5 =
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dp.TIM5.timer(1.khz(), ccdr.peripheral.TIM5, &ccdr.clocks);
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// Configure the timer to count at the designed tick rate. We will manually set the
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// period below.
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timer5.pause();
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timer5.set_tick_freq(design_parameters::TIMER_FREQUENCY);
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// The time stamp timer must run at exactly a multiple of the sample timer based on the
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// batch size. To accomodate this, we manually set the prescaler identical to the sample
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// timer, but use a period that is longer.
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let mut timer = timers::TimestampTimer::new(timer5);
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let period =
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digital_input_stamper::calculate_timestamp_timer_period();
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timer.set_period_ticks(period);
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timer
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};
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let timestamp_timer_channels = timestamp_timer.channels();
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// Configure the SPI interfaces to the ADCs and DACs.
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let adcs = {
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let adc0 = {
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@ -317,7 +355,7 @@ const APP: () = {
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let spi: hal::spi::Spi<_, _, u16> = dp.SPI2.spi(
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(spi_sck, spi_miso, hal::spi::NoMosi),
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config,
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design_parameters::ADC_DAC_SCK_MHZ_MAX.mhz(),
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design_parameters::ADC_DAC_SCK_MAX,
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ccdr.peripheral.SPI2,
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&ccdr.clocks,
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);
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@ -355,7 +393,7 @@ const APP: () = {
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let spi: hal::spi::Spi<_, _, u16> = dp.SPI3.spi(
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(spi_sck, spi_miso, hal::spi::NoMosi),
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config,
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design_parameters::ADC_DAC_SCK_MHZ_MAX.mhz(),
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design_parameters::ADC_DAC_SCK_MAX,
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ccdr.peripheral.SPI3,
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&ccdr.clocks,
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);
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@ -405,7 +443,7 @@ const APP: () = {
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dp.SPI4.spi(
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(spi_sck, spi_miso, hal::spi::NoMosi),
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config,
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design_parameters::ADC_DAC_SCK_MHZ_MAX.mhz(),
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design_parameters::ADC_DAC_SCK_MAX,
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ccdr.peripheral.SPI4,
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&ccdr.clocks,
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)
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@ -437,7 +475,7 @@ const APP: () = {
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dp.SPI5.spi(
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(spi_sck, spi_miso, hal::spi::NoMosi),
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config,
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design_parameters::ADC_DAC_SCK_MHZ_MAX.mhz(),
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design_parameters::ADC_DAC_SCK_MAX,
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ccdr.peripheral.SPI5,
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&ccdr.clocks,
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)
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@ -507,7 +545,7 @@ const APP: () = {
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let qspi = hal::qspi::Qspi::bank2(
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dp.QUADSPI,
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qspi_pins,
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40.mhz(),
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design_parameters::POUNDER_QSPI_FREQUENCY,
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&ccdr.clocks,
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ccdr.peripheral.QSPI,
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);
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@ -629,25 +667,26 @@ const APP: () = {
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ccdr.peripheral.HRTIM,
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);
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// IO_Update should be latched for 4 SYNC_CLK cycles after the QSPI profile
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// write. With pounder SYNC_CLK running at 100MHz (1/4 of the pounder reference
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// clock of 400MHz), this corresponds to 40ns. To accomodate rounding errors, we
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// use 50ns instead.
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//
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// Profile writes are always 16 bytes, with 2 cycles required per byte, coming
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// out to a total of 32 QSPI clock cycles. The QSPI is configured for 40MHz, so
|
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// this comes out to an offset of 800nS. We use 900ns to be safe - note that the
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// timer is triggered after the QSPI write, which can take approximately 120nS,
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// so there is additional margin.
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// IO_Update occurs after a fixed delay from the QSPI write. Note that the timer
|
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// is triggered after the QSPI write, which can take approximately 120nS, so
|
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// there is additional margin.
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hrtimer.configure_single_shot(
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hrtimer::Channel::Two,
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50_e-9,
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900_e-9,
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design_parameters::POUNDER_IO_UPDATE_DURATION,
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design_parameters::POUNDER_IO_UPDATE_DELAY,
|
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);
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||||
|
||||
// Ensure that we have enough time for an IO-update every sample.
|
||||
let sample_frequency = {
|
||||
let timer_frequency: hal::time::Hertz =
|
||||
design_parameters::TIMER_FREQUENCY.into();
|
||||
timer_frequency.0 as f32 / ADC_SAMPLE_TICKS as f32
|
||||
};
|
||||
|
||||
let sample_period = 1.0 / sample_frequency;
|
||||
assert!(
|
||||
1.0 / (1000 * SAMPLE_FREQUENCY_KHZ) as f32 > 900_e-9
|
||||
sample_period
|
||||
> design_parameters::POUNDER_IO_UPDATE_DELAY
|
||||
);
|
||||
|
||||
hrtimer
|
||||
|
|
@ -781,14 +820,25 @@ const APP: () = {
|
|||
// Utilize the cycle counter for RTIC scheduling.
|
||||
cp.DWT.enable_cycle_counter();
|
||||
|
||||
let mut input_stamper = {
|
||||
let trigger = gpioa.pa3.into_alternate_af2();
|
||||
digital_input_stamper::InputStamper::new(
|
||||
trigger,
|
||||
timestamp_timer_channels.ch4,
|
||||
)
|
||||
};
|
||||
|
||||
// Start sampling ADCs.
|
||||
sampling_timer.start();
|
||||
timestamp_timer.start();
|
||||
input_stamper.start();
|
||||
|
||||
init::LateResources {
|
||||
afes: (afe0, afe1),
|
||||
|
||||
adcs,
|
||||
dacs,
|
||||
input_stamper,
|
||||
dds_output,
|
||||
pounder: pounder_devices,
|
||||
|
||||
|
|
@ -799,7 +849,7 @@ const APP: () = {
|
|||
}
|
||||
}
|
||||
|
||||
#[task(binds=DMA1_STR3, resources=[adcs, dacs, iir_state, iir_ch, dds_output], priority=2)]
|
||||
#[task(binds=DMA1_STR3, resources=[adcs, dacs, iir_state, iir_ch, dds_output, input_stamper], priority=2)]
|
||||
fn process(c: process::Context) {
|
||||
let adc_samples = [
|
||||
c.resources.adcs.0.acquire_buffer(),
|
||||
|
|
@ -810,6 +860,8 @@ const APP: () = {
|
|||
c.resources.dacs.1.acquire_buffer(),
|
||||
];
|
||||
|
||||
let _timestamp = c.resources.input_stamper.latest_timestamp();
|
||||
|
||||
for channel in 0..adc_samples.len() {
|
||||
for sample in 0..adc_samples[0].len() {
|
||||
let x = f32::from(adc_samples[channel][sample] as i16);
|
||||
|
|
|
|||
|
|
@ -1,119 +0,0 @@
|
|||
///! The sampling timer is used for managing ADC sampling and external reference timestamping.
|
||||
use super::hal;
|
||||
|
||||
/// The timer used for managing ADC sampling.
|
||||
pub struct SamplingTimer {
|
||||
timer: hal::timer::Timer<hal::stm32::TIM2>,
|
||||
channels: Option<tim2::Channels>,
|
||||
}
|
||||
|
||||
impl SamplingTimer {
|
||||
/// Construct the sampling timer.
|
||||
pub fn new(mut timer: hal::timer::Timer<hal::stm32::TIM2>) -> Self {
|
||||
timer.pause();
|
||||
|
||||
Self {
|
||||
timer,
|
||||
// Note(unsafe): Once these channels are taken, we guarantee that we do not modify any
|
||||
// of the underlying timer channel registers, as ownership of the channels is now
|
||||
// provided through the associated channel structures. We additionally guarantee this
|
||||
// can only be called once because there is only one Timer2 and this resource takes
|
||||
// ownership of it once instantiated.
|
||||
channels: unsafe { Some(tim2::Channels::new()) },
|
||||
}
|
||||
}
|
||||
|
||||
/// Get the timer capture/compare channels.
|
||||
pub fn channels(&mut self) -> tim2::Channels {
|
||||
self.channels.take().unwrap()
|
||||
}
|
||||
|
||||
/// Start the sampling timer.
|
||||
pub fn start(&mut self) {
|
||||
self.timer.reset_counter();
|
||||
self.timer.resume();
|
||||
}
|
||||
}
|
||||
|
||||
macro_rules! timer_channel {
|
||||
($name:ident, $TY:ty, ($ccxde:expr, $ccrx:expr, $ccmrx_output:expr, $ccxs:expr)) => {
|
||||
pub struct $name {}
|
||||
|
||||
paste::paste! {
|
||||
impl $name {
|
||||
/// Construct a new timer channel.
|
||||
///
|
||||
/// Note(unsafe): This function must only be called once. Once constructed, the
|
||||
/// constructee guarantees to never modify the timer channel.
|
||||
unsafe fn new() -> Self {
|
||||
Self {}
|
||||
}
|
||||
|
||||
/// Allow CH4 to generate DMA requests.
|
||||
pub fn listen_dma(&self) {
|
||||
let regs = unsafe { &*<$TY>::ptr() };
|
||||
regs.dier.modify(|_, w| w.[< $ccxde >]().set_bit());
|
||||
}
|
||||
|
||||
/// Operate CH2 as an output-compare.
|
||||
///
|
||||
/// # Args
|
||||
/// * `value` - The value to compare the sampling timer's counter against.
|
||||
pub fn to_output_compare(&self, value: u32) {
|
||||
let regs = unsafe { &*<$TY>::ptr() };
|
||||
assert!(value <= regs.arr.read().bits());
|
||||
regs.[< $ccrx >].write(|w| w.ccr().bits(value));
|
||||
regs.[< $ccmrx_output >]()
|
||||
.modify(|_, w| unsafe { w.[< $ccxs >]().bits(0) });
|
||||
}
|
||||
}
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
pub mod tim2 {
|
||||
use stm32h7xx_hal as hal;
|
||||
|
||||
/// The channels representing the timer.
|
||||
pub struct Channels {
|
||||
pub ch1: Channel1,
|
||||
pub ch2: Channel2,
|
||||
pub ch3: Channel3,
|
||||
pub ch4: Channel4,
|
||||
}
|
||||
|
||||
impl Channels {
|
||||
/// Construct a new set of channels.
|
||||
///
|
||||
/// Note(unsafe): This is only safe to call once.
|
||||
pub unsafe fn new() -> Self {
|
||||
Self {
|
||||
ch1: Channel1::new(),
|
||||
ch2: Channel2::new(),
|
||||
ch3: Channel3::new(),
|
||||
ch4: Channel4::new(),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
timer_channel!(
|
||||
Channel1,
|
||||
hal::stm32::TIM2,
|
||||
(cc1de, ccr1, ccmr1_output, cc1s)
|
||||
);
|
||||
timer_channel!(
|
||||
Channel2,
|
||||
hal::stm32::TIM2,
|
||||
(cc2de, ccr2, ccmr1_output, cc1s)
|
||||
);
|
||||
timer_channel!(
|
||||
Channel3,
|
||||
hal::stm32::TIM2,
|
||||
(cc3de, ccr3, ccmr2_output, cc3s)
|
||||
);
|
||||
timer_channel!(
|
||||
Channel4,
|
||||
hal::stm32::TIM2,
|
||||
(cc4de, ccr4, ccmr2_output, cc4s)
|
||||
);
|
||||
}
|
||||
|
|
@ -0,0 +1,221 @@
|
|||
///! The sampling timer is used for managing ADC sampling and external reference timestamping.
|
||||
use super::hal;
|
||||
|
||||
macro_rules! timer_channels {
|
||||
($name:ident, $TY:ident, u32) => {
|
||||
paste::paste! {
|
||||
|
||||
/// The timer used for managing ADC sampling.
|
||||
pub struct $name {
|
||||
timer: hal::timer::Timer<hal::stm32::[< $TY >]>,
|
||||
channels: Option<[< $TY:lower >]::Channels>,
|
||||
}
|
||||
|
||||
impl $name {
|
||||
/// Construct the sampling timer.
|
||||
pub fn new(mut timer: hal::timer::Timer<hal::stm32::[< $TY>]>) -> Self {
|
||||
timer.pause();
|
||||
|
||||
Self {
|
||||
timer,
|
||||
// Note(unsafe): Once these channels are taken, we guarantee that we do not modify any
|
||||
// of the underlying timer channel registers, as ownership of the channels is now
|
||||
// provided through the associated channel structures. We additionally guarantee this
|
||||
// can only be called once because there is only one Timer2 and this resource takes
|
||||
// ownership of it once instantiated.
|
||||
channels: unsafe { Some([< $TY:lower >]::Channels::new()) },
|
||||
}
|
||||
}
|
||||
|
||||
/// Get the timer capture/compare channels.
|
||||
pub fn channels(&mut self) -> [< $TY:lower >]::Channels {
|
||||
self.channels.take().unwrap()
|
||||
}
|
||||
|
||||
/// Get the period of the timer.
|
||||
#[allow(dead_code)]
|
||||
pub fn get_period(&self) -> u32 {
|
||||
let regs = unsafe { &*hal::stm32::$TY::ptr() };
|
||||
regs.arr.read().arr().bits()
|
||||
}
|
||||
|
||||
/// Manually set the period of the timer.
|
||||
#[allow(dead_code)]
|
||||
pub fn set_period_ticks(&mut self, period: u32) {
|
||||
let regs = unsafe { &*hal::stm32::$TY::ptr() };
|
||||
regs.arr.write(|w| w.arr().bits(period));
|
||||
}
|
||||
|
||||
/// Start the timer.
|
||||
pub fn start(mut self) {
|
||||
// Force a refresh of the frequency settings.
|
||||
self.timer.apply_freq();
|
||||
|
||||
self.timer.reset_counter();
|
||||
self.timer.resume();
|
||||
}
|
||||
}
|
||||
|
||||
pub mod [< $TY:lower >] {
|
||||
pub use hal::stm32::tim2::ccmr1_input::{CC1S_A, CC2S_A};
|
||||
pub use hal::stm32::tim2::ccmr2_input::{CC3S_A, CC4S_A};
|
||||
|
||||
use stm32h7xx_hal as hal;
|
||||
use hal::dma::{traits::TargetAddress, PeripheralToMemory, dma::DMAReq};
|
||||
use hal::stm32::$TY;
|
||||
|
||||
/// The channels representing the timer.
|
||||
pub struct Channels {
|
||||
pub ch1: Channel1,
|
||||
pub ch2: Channel2,
|
||||
pub ch3: Channel3,
|
||||
pub ch4: Channel4,
|
||||
}
|
||||
|
||||
impl Channels {
|
||||
/// Construct a new set of channels.
|
||||
///
|
||||
/// Note(unsafe): This is only safe to call once.
|
||||
pub unsafe fn new() -> Self {
|
||||
Self {
|
||||
ch1: Channel1::new(),
|
||||
ch2: Channel2::new(),
|
||||
ch3: Channel3::new(),
|
||||
ch4: Channel4::new(),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
timer_channels!(1, $TY, ccmr1);
|
||||
timer_channels!(2, $TY, ccmr1);
|
||||
timer_channels!(3, $TY, ccmr2);
|
||||
timer_channels!(4, $TY, ccmr2);
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
($index:expr, $TY:ty, $ccmrx:expr) => {
|
||||
paste::paste! {
|
||||
/// A capture/compare channel of the timer.
|
||||
pub struct [< Channel $index >] {}
|
||||
|
||||
/// A capture channel of the timer.
|
||||
pub struct [< Channel $index InputCapture>] {}
|
||||
|
||||
impl [< Channel $index >] {
|
||||
/// Construct a new timer channel.
|
||||
///
|
||||
/// Note(unsafe): This function must only be called once. Once constructed, the
|
||||
/// constructee guarantees to never modify the timer channel.
|
||||
unsafe fn new() -> Self {
|
||||
Self {}
|
||||
}
|
||||
|
||||
/// Allow the channel to generate DMA requests.
|
||||
#[allow(dead_code)]
|
||||
pub fn listen_dma(&self) {
|
||||
let regs = unsafe { &*<$TY>::ptr() };
|
||||
regs.dier.modify(|_, w| w.[< cc $index de >]().set_bit());
|
||||
}
|
||||
|
||||
/// Operate the channel as an output-compare.
|
||||
///
|
||||
/// # Args
|
||||
/// * `value` - The value to compare the sampling timer's counter against.
|
||||
#[allow(dead_code)]
|
||||
pub fn to_output_compare(&self, value: u32) {
|
||||
let regs = unsafe { &*<$TY>::ptr() };
|
||||
assert!(value <= regs.arr.read().bits());
|
||||
regs.[< ccr $index >].write(|w| w.ccr().bits(value));
|
||||
regs.[< $ccmrx _output >]()
|
||||
.modify(|_, w| unsafe { w.[< cc $index s >]().bits(0) });
|
||||
}
|
||||
|
||||
/// Operate the channel in input-capture mode.
|
||||
///
|
||||
/// # Args
|
||||
/// * `input` - The input source for the input capture event.
|
||||
#[allow(dead_code)]
|
||||
pub fn into_input_capture(self, input: hal::stm32::tim2::[< $ccmrx _input >]::[< CC $index S_A >]) -> [< Channel $index InputCapture >]{
|
||||
let regs = unsafe { &*<$TY>::ptr() };
|
||||
regs.[< $ccmrx _input >]().modify(|_, w| w.[< cc $index s>]().variant(input));
|
||||
|
||||
[< Channel $index InputCapture >] {}
|
||||
}
|
||||
}
|
||||
|
||||
impl [< Channel $index InputCapture >] {
|
||||
/// Get the latest capture from the channel.
|
||||
#[allow(dead_code)]
|
||||
pub fn latest_capture(&mut self) -> Result<Option<u32>, ()> {
|
||||
// Note(unsafe): This channel owns all access to the specific timer channel.
|
||||
// Only atomic operations on completed on the timer registers.
|
||||
let regs = unsafe { &*<$TY>::ptr() };
|
||||
let sr = regs.sr.read();
|
||||
|
||||
let result = if sr.[< cc $index if >]().bit_is_set() {
|
||||
// Read the capture value. Reading the captured value clears the flag in the
|
||||
// status register automatically.
|
||||
let ccx = regs.[< ccr $index >].read();
|
||||
Some(ccx.ccr().bits())
|
||||
} else {
|
||||
None
|
||||
};
|
||||
|
||||
// Read SR again to check for a potential over-capture. If there is an
|
||||
// overcapture, return an error.
|
||||
if regs.sr.read().[< cc $index of >]().bit_is_clear() {
|
||||
Ok(result)
|
||||
} else {
|
||||
regs.sr.modify(|_, w| w.[< cc $index of >]().clear_bit());
|
||||
Err(())
|
||||
}
|
||||
}
|
||||
|
||||
/// Allow the channel to generate DMA requests.
|
||||
#[allow(dead_code)]
|
||||
pub fn listen_dma(&self) {
|
||||
// Note(unsafe): This channel owns all access to the specific timer channel.
|
||||
// Only atomic operations on completed on the timer registers.
|
||||
let regs = unsafe { &*<$TY>::ptr() };
|
||||
regs.dier.modify(|_, w| w.[< cc $index de >]().set_bit());
|
||||
}
|
||||
|
||||
/// Enable the input capture to begin capturing timer values.
|
||||
#[allow(dead_code)]
|
||||
pub fn enable(&mut self) {
|
||||
// Note(unsafe): This channel owns all access to the specific timer channel.
|
||||
// Only atomic operations on completed on the timer registers.
|
||||
let regs = unsafe { &*<$TY>::ptr() };
|
||||
regs.ccer.modify(|_, w| w.[< cc $index e >]().set_bit());
|
||||
}
|
||||
|
||||
/// Check if an over-capture event has occurred.
|
||||
#[allow(dead_code)]
|
||||
pub fn check_overcapture(&self) -> bool {
|
||||
// Note(unsafe): This channel owns all access to the specific timer channel.
|
||||
// Only atomic operations on completed on the timer registers.
|
||||
let regs = unsafe { &*<$TY>::ptr() };
|
||||
regs.sr.read().[< cc $index of >]().bit_is_set()
|
||||
}
|
||||
}
|
||||
|
||||
// Note(unsafe): This manually implements DMA support for input-capture channels. This
|
||||
// is safe as it is only completed once per channel and each DMA request is allocated to
|
||||
// each channel as the owner.
|
||||
unsafe impl TargetAddress<PeripheralToMemory> for [< Channel $index InputCapture >] {
|
||||
type MemSize = u32;
|
||||
|
||||
const REQUEST_LINE: Option<u8> = Some(DMAReq::[< $TY _CH $index >]as u8);
|
||||
|
||||
fn address(&self) -> u32 {
|
||||
let regs = unsafe { &*<$TY>::ptr() };
|
||||
®s.[<ccr $index >] as *const _ as u32
|
||||
}
|
||||
}
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
timer_channels!(SamplingTimer, TIM2, u32);
|
||||
timer_channels!(TimestampTimer, TIM5, u32);
|
||||
Loading…
Reference in New Issue