experiment with duplex adc xfers
problematic because: * in tsize=1 there needs to be a cstart * in tsize=0 there is no mssi
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a2265ab2d1
42
src/main.rs
42
src/main.rs
@ -183,7 +183,6 @@ fn rcc_pll_setup(rcc: &stm32::RCC, flash: &stm32::FLASH) {
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}
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}
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fn io_compensation_setup(syscfg: &stm32::SYSCFG) {
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fn io_compensation_setup(syscfg: &stm32::SYSCFG) {
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// enable I/O compensation cell
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syscfg.cccsr.modify(|_, w|
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syscfg.cccsr.modify(|_, w|
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w.en().set_bit()
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w.en().set_bit()
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.cs().clear_bit()
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.cs().clear_bit()
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@ -224,8 +223,8 @@ fn gpio_setup(gpioa: &stm32::GPIOA, gpiob: &stm32::GPIOB, gpiod: &stm32::GPIOD,
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.moder3().output()
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.moder3().output()
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);
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);
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gpiog.odr.modify(|_, w|
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gpiog.odr.modify(|_, w|
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w.odr2().set_bit()
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w.odr2().clear_bit()
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.odr3().set_bit()
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.odr3().clear_bit()
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);
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);
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// SCK: PG11
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// SCK: PG11
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@ -287,13 +286,13 @@ fn spi1_setup(spi1: &stm32::SPI1) {
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.lsbfrst().clear_bit()
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.lsbfrst().clear_bit()
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.master().set_bit()
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.master().set_bit()
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.sp().bits(0) // motorola
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.sp().bits(0) // motorola
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.comm().bits(0b10) // simplex receiver
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.comm().bits(0b00) // duplex
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.ioswp().clear_bit()
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.ioswp().clear_bit()
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.midi().bits(0) // master inter data idle
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.midi().bits(0) // master inter data idle
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.mssi().bits(11) // master SS idle
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.mssi().bits(11) // master SS idle
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});
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});
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spi1.cr2.modify(|_, w| unsafe {
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spi1.cr2.modify(|_, w| unsafe {
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w.tsize().bits(1)
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w.tsize().bits(0)
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});
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});
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spi1.cr1.write(|w| w.spe().set_bit());
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spi1.cr1.write(|w| w.spe().set_bit());
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}
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}
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@ -367,31 +366,28 @@ fn main() -> ! {
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let spi2 = dp.SPI2;
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let spi2 = dp.SPI2;
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spi2_setup(&spi2);
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spi2_setup(&spi2);
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// at least one SCK between EOT and CSTART
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spi1.cr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 9)) });
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// at least one SCK between EOT and CSTART
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// at least one SCK between EOT and CSTART
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spi2.cr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 9)) });
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spi2.cr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 9)) });
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let txdr = &spi2.txdr as *const _ as *mut u16;
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// needs to be a half word write
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let rxdr = &spi1.rxdr as *const _ as *const u16;
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let txdr1 = &spi1.txdr as *const _ as *mut u16;
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let rxdr1 = &spi1.rxdr as *const _ as *const u16;
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// needs to be a half word write
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let txdr2 = &spi2.txdr as *const _ as *mut u16;
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loop {
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loop {
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#[cfg(feature = "bkpt")]
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#[cfg(feature = "bkpt")]
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cortex_m::asm::bkpt();
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cortex_m::asm::bkpt();
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// at least one SCK between EOT and CSTART
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while spi1.sr.read().txp().bit_is_clear() {}
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spi1.cr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 9)) });
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unsafe { ptr::write_volatile(txdr1, 0) };
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while spi1.sr.read().eot().bit_is_clear() {}
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// while spi1.sr.read().txc().bit_is_clear() {}
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spi1.ifcr.write(|w| w.eotc().set_bit());
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while spi1.sr.read().rxp().bit_is_clear() {}
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if spi1.sr.read().rxp().bit_is_clear() {
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let a = unsafe { ptr::read_volatile(rxdr1) };
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continue;
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while spi2.sr.read().txp().bit_is_clear() {}
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}
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unsafe { ptr::write_volatile(txdr2, a ^ 0x8000) };
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let a = unsafe { ptr::read_volatile(rxdr) };
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// while spi2.sr.read().txc().bit_is_clear() {}
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let d = a ^ 0x8000;
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if spi2.sr.read().txp().bit_is_clear() {
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continue;
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}
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// needs to be a half word write
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unsafe { ptr::write_volatile(txdr, d) };
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while spi2.sr.read().txc().bit_is_clear() {}
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#[cfg(feature = "bkpt")]
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#[cfg(feature = "bkpt")]
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cortex_m::asm::bkpt();
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cortex_m::asm::bkpt();
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