Adding updates after review
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@ -56,7 +56,7 @@ pub fn calculate_timestamp_timer_period() -> u32 {
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// period of the timestamp timer. The period is always 1 larger than the value configured in the
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// register.
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let period: u64 = batch_duration_ticks * j - 1u64;
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assert!(period < u32::MAX as u64);
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assert!(period <= u32::MAX as u64);
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period as u32
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}
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@ -677,10 +677,11 @@ const APP: () = {
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);
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// Ensure that we have enough time for an IO-update every sample.
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let sample_frequency = (design_parameters::TIMER_FREQUENCY.0
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as f32
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* 1_000_000.0)
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/ ADC_SAMPLE_TICKS as f32;
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let sample_frequency = {
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let timer_frequency: hal::time::Hertz =
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design_parameters::TIMER_FREQUENCY.into();
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timer_frequency.0 as f32 / ADC_SAMPLE_TICKS as f32
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};
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let sample_period = 1.0 / sample_frequency;
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assert!(
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@ -152,19 +152,22 @@ macro_rules! timer_channels {
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// Only atomic operations on completed on the timer registers.
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let regs = unsafe { &*<$TY>::ptr() };
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let sr = regs.sr.read();
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let ccx = regs.[< ccr $index >].read();
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let result = if sr.[< cc $index if >]().bit_is_set() {
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regs.sr.modify(|_, w| w.[< cc $index if >]().clear_bit());
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// Read the capture value. Reading the captured value clears the flag in the
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// status register automatically.
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let ccx = regs.[< ccr $index >].read();
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Some(ccx.ccr().bits())
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} else {
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None
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};
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// If there is an overcapture, return an error.
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if sr.[< cc $index of >]().bit_is_clear() {
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// Read SR again to check for a potential over-capture. If there is an
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// overcapture, return an error.
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if regs.sr.read().[< cc $index of >]().bit_is_clear() {
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Ok(result)
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} else {
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regs.sr.modify(|_, w| w.[< cc $index of >]().clear_bit());
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Err(())
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}
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}
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