Adding signal generator control to dual-iir
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@ -16,6 +16,7 @@ use stabilizer::{
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hal,
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hal,
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system_timer::SystemTimer,
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system_timer::SystemTimer,
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DigitalInput0, DigitalInput1, AFE0, AFE1,
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DigitalInput0, DigitalInput1, AFE0, AFE1,
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signal_generator::SignalGenerator,
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},
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},
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net::{
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net::{
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data_stream::{BlockGenerator, StreamTarget},
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data_stream::{BlockGenerator, StreamTarget},
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@ -39,6 +40,13 @@ pub struct Settings {
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force_hold: bool,
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force_hold: bool,
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telemetry_period: u16,
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telemetry_period: u16,
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stream_target: StreamTarget,
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stream_target: StreamTarget,
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signal_generator: signal_generator::Config;
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output_mode: [OutputMode; 2],
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}
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pub struct OutputMode {
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IirFilter,
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SignalGenerator,
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}
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}
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impl Default for Settings {
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impl Default for Settings {
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@ -59,6 +67,8 @@ impl Default for Settings {
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// The default telemetry period in seconds.
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// The default telemetry period in seconds.
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telemetry_period: 10,
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telemetry_period: 10,
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signal_generator: signal_generator::Config::default(),
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stream_target: StreamTarget::default(),
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stream_target: StreamTarget::default(),
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}
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}
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}
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}
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@ -172,6 +182,8 @@ const APP: () = {
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fence(Ordering::SeqCst);
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fence(Ordering::SeqCst);
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for channel in 0..adc_samples.len() {
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for channel in 0..adc_samples.len() {
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match settings.output_mode[channel] {
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OutputMode::IirFilter => {
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adc_samples[channel]
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adc_samples[channel]
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.iter()
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.iter()
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.zip(dac_samples[channel].iter_mut())
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.zip(dac_samples[channel].iter_mut())
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@ -191,6 +203,22 @@ const APP: () = {
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})
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})
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.last();
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.last();
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}
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}
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OutputMode::SignalGenerator => {
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// Do not generate the samples twice, or we may mess up phasing of the
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// signal generator. Instead, copy the previously-generated signal.
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// TODO: Is there a nicer way we can handle this edge case?
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if (channel == 1) && settings.output_mode[0] == OutputMode::SignalGenerator {
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adc_samples[1].copy_from_slice(adc_samples[0]);
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} else {
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signal_generator.generate(&mut adc_samples[channel]);
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}
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}
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}
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}
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if !settings.output_mode.iter().any(|&mode| mode == OutputMode::SignalGenerator) {
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signal_generator.skip(adc_samples[0].len());
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}
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// Stream the data.
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// Stream the data.
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generator.send(&adc_samples, &dac_samples);
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generator.send(&adc_samples, &dac_samples);
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@ -230,6 +258,9 @@ const APP: () = {
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c.resources.afes.0.set_gain(settings.afe[0]);
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c.resources.afes.0.set_gain(settings.afe[0]);
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c.resources.afes.1.set_gain(settings.afe[1]);
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c.resources.afes.1.set_gain(settings.afe[1]);
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// Update the signal generator
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c.resources.signal_generator.update_waveform(settings.signal_generator);
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let target = settings.stream_target.into();
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let target = settings.stream_target.into();
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c.resources.network.direct_stream(target);
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c.resources.network.direct_stream(target);
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}
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}
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@ -66,13 +66,13 @@ struct InternalConf {
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}
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}
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#[derive(Debug)]
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#[derive(Debug)]
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pub struct Generator {
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pub struct SignalGenerator {
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index: u32,
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index: u32,
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config: InternalConf,
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config: InternalConf,
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pending_config: Option<InternalConf>,
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pending_config: Option<InternalConf>,
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}
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}
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impl Default for Generator {
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impl Default for SignalGenerator {
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fn default() -> Self {
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fn default() -> Self {
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Self {
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Self {
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config: Config::default().into(),
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config: Config::default().into(),
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@ -82,7 +82,7 @@ impl Default for Generator {
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}
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}
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}
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}
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impl Generator {
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impl SignalGenerator {
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/// Construct a new signal generator with some specific config.
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/// Construct a new signal generator with some specific config.
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///
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///
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/// # Args
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/// # Args
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@ -108,6 +108,18 @@ impl Generator {
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}
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}
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}
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}
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/// Skip `count` elements of the generator
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pub fn skip(&mut self, count: usize) {
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let index = self.index.wrapping_add(count);
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// If we skip past the period of the signal, apply any pending config.
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if index > self.config.period && let Some(config) = self.pendig_config.take() {
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self.config = config;
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}
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self.index = index % self.config.period;
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}
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/// Get the next value in the generator sequence.
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/// Get the next value in the generator sequence.
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pub fn next(&mut self) -> i16 {
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pub fn next(&mut self) -> i16 {
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// When phase wraps, apply any new settings.
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// When phase wraps, apply any new settings.
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