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cleanup

This commit is contained in:
Robert Jördens 2019-04-28 20:44:38 +02:00
parent 0efd14aec8
commit 9863ba3a33
2 changed files with 54 additions and 56 deletions
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52
src/eth.rs
View File

@ -21,7 +21,7 @@ mod phy_consts {
pub const PHY_REG_CTL: u8 = 0x0D; // Ethernet PHY Register Control pub const PHY_REG_CTL: u8 = 0x0D; // Ethernet PHY Register Control
pub const PHY_REG_ADDAR: u8 = 0x0E; // Ethernet PHY Address or Data pub const PHY_REG_ADDAR: u8 = 0x0E; // Ethernet PHY Address or Data
pub const PHY_REG_WUCSR: u16 = 08010; pub const PHY_REG_WUCSR: u16 = 0x8010;
pub const PHY_REG_BCR_COLTEST: u16 = 1 << 7; pub const PHY_REG_BCR_COLTEST: u16 = 1 << 7;
pub const PHY_REG_BCR_FD: u16 = 1 << 8; pub const PHY_REG_BCR_FD: u16 = 1 << 8;
@ -47,25 +47,25 @@ mod phy_consts {
} }
use self::phy_consts::*; use self::phy_consts::*;
pub const MTU: usize = 1522; pub const MTU: usize = 1536;
const EMAC_DES3_OWN: u32 = 0x80000000; const EMAC_DES3_OWN: u32 = 0x8000_0000;
const EMAC_DES3_CTXT: u32 = 0x40000000; const EMAC_DES3_CTXT: u32 = 0x4000_0000;
const EMAC_DES3_FD: u32 = 0x20000000; const EMAC_DES3_FD: u32 = 0x2000_0000;
const EMAC_DES3_LD: u32 = 0x10000000; const EMAC_DES3_LD: u32 = 0x1000_0000;
const EMAC_DES3_ES: u32 = 0x00008000; const EMAC_DES3_ES: u32 = 0x0000_8000;
const EMAC_TDES2_IOC: u32 = 0x80000000; const EMAC_TDES2_IOC: u32 = 0x8000_0000;
const EMAC_RDES3_IOC: u32 = 0x40000000; const EMAC_RDES3_IOC: u32 = 0x4000_0000;
const EMAC_RDES3_PL: u32 = 0x00007FFF; const EMAC_RDES3_PL: u32 = 0x0000_7FFF;
const EMAC_RDES3_BUF1V: u32 = 0x01000000; const EMAC_RDES3_BUF1V: u32 = 0x0100_0000;
const EMAC_TDES2_B1L: u32 = 0x00003FFF; const EMAC_TDES2_B1L: u32 = 0x0000_3FFF;
const EMAC_DES0_BUF1AP: u32 = 0xFFFFFFFF; const EMAC_DES0_BUF1AP: u32 = 0xFFFF_FFFF;
const ETH_DESC_U32_SIZE: usize = 4; const ETH_DESC_U32_SIZE: usize = 4;
const ETH_TX_BUFFER_COUNT: usize = 4; const ETH_TX_BUFFER_COUNT: usize = 4;
const ETH_TX_BUFFER_SIZE: usize = 1536; const ETH_TX_BUFFER_SIZE: usize = MTU;
const ETH_RX_BUFFER_COUNT: usize = 4; const ETH_RX_BUFFER_COUNT: usize = 4;
const ETH_RX_BUFFER_SIZE: usize = 1536; const ETH_RX_BUFFER_SIZE: usize = MTU;
#[allow(dead_code)] #[allow(dead_code)]
mod cr_consts { mod cr_consts {
@ -403,14 +403,14 @@ impl Device {
}); });
// Set the MAC address // Set the MAC address
eth_mac.maca0lr.write(|w| eth_mac.maca0lr.write(|w|
w.addrlo().bits( mac.0[0] as u32 | w.addrlo().bits( u32::from(mac.0[0]) |
((mac.0[1] as u32) << 8) | (u32::from(mac.0[1]) << 8) |
((mac.0[2] as u32) << 16) | (u32::from(mac.0[2]) << 16) |
((mac.0[3] as u32) << 24)) (u32::from(mac.0[3]) << 24))
); );
eth_mac.maca0hr.write(|w| eth_mac.maca0hr.write(|w|
w.addrhi().bits( mac.0[4] as u16 | w.addrhi().bits( u16::from(mac.0[4]) |
((mac.0[5] as u16) << 8)) (u16::from(mac.0[5]) << 8))
.ae().set_bit() .ae().set_bit()
//.sa().clear_bit() //.sa().clear_bit()
//.mbc().bits(0b000000) //.mbc().bits(0b000000)
@ -543,7 +543,7 @@ impl<'a, 'b> phy::Device<'a> for &'b mut Device {
fn capabilities(&self) -> phy::DeviceCapabilities { fn capabilities(&self) -> phy::DeviceCapabilities {
let mut capabilities = phy::DeviceCapabilities::default(); let mut capabilities = phy::DeviceCapabilities::default();
capabilities.max_transmission_unit = 1500; capabilities.max_transmission_unit = 1514;
capabilities.max_burst_size = Some(self.tx.desc_buf.len()); capabilities.max_burst_size = Some(self.tx.desc_buf.len());
capabilities capabilities
} }
@ -592,7 +592,8 @@ impl<'a> phy::TxToken for TxToken<'a> {
} }
} }
pub fn eth_interrupt_handler(eth_dma: &stm32::ETHERNET_DMA) { pub unsafe fn interrupt_handler() {
let eth_dma = &*stm32::ETHERNET_DMA::ptr();
eth_dma.dmacsr.write(|w| eth_dma.dmacsr.write(|w|
w w
.nis().set_bit() .nis().set_bit()
@ -601,8 +602,9 @@ pub fn eth_interrupt_handler(eth_dma: &stm32::ETHERNET_DMA) {
); );
} }
pub fn enable_interrupt(dma: &stm32::ETHERNET_DMA) { pub unsafe fn enable_interrupt() {
dma.dmacier.modify(|_, w| let eth_dma = &*stm32::ETHERNET_DMA::ptr();
eth_dma.dmacier.modify(|_, w|
w w
.nie().set_bit() .nie().set_bit()
.rie().set_bit() .rie().set_bit()

58
src/main.rs
View File

@ -335,7 +335,7 @@ fn spi1_setup(spi1: &stm32::SPI1) {
spi1.cfg1.modify(|_, w| { spi1.cfg1.modify(|_, w| {
w.mbr().bits(1) // clk/4 w.mbr().bits(1) // clk/4
.dsize().bits(16 - 1) .dsize().bits(16 - 1)
.fthvl().bits(1 - 1) // one data .fthvl().one_frame()
}); });
spi1.cfg2.modify(|_, w| unsafe { spi1.cfg2.modify(|_, w| unsafe {
w.afcntr().set_bit() w.afcntr().set_bit()
@ -364,7 +364,7 @@ fn spi5_setup(spi5: &stm32::SPI5) {
spi5.cfg1.modify(|_, w| { spi5.cfg1.modify(|_, w| {
w.mbr().bits(1) // clk/4 w.mbr().bits(1) // clk/4
.dsize().bits(16 - 1) .dsize().bits(16 - 1)
.fthvl().bits(1 - 1) // one data .fthvl().one_frame()
}); });
spi5.cfg2.modify(|_, w| unsafe { spi5.cfg2.modify(|_, w| unsafe {
w.afcntr().set_bit() w.afcntr().set_bit()
@ -393,7 +393,7 @@ fn spi2_setup(spi2: &stm32::SPI2) {
spi2.cfg1.modify(|_, w| { spi2.cfg1.modify(|_, w| {
w.mbr().bits(0) // clk/2 w.mbr().bits(0) // clk/2
.dsize().bits(16 - 1) .dsize().bits(16 - 1)
.fthvl().bits(1 - 1) // one data .fthvl().one_frame()
}); });
spi2.cfg2.modify(|_, w| unsafe { spi2.cfg2.modify(|_, w| unsafe {
w.afcntr().set_bit() w.afcntr().set_bit()
@ -411,11 +411,9 @@ fn spi2_setup(spi2: &stm32::SPI2) {
.midi().bits(0) // master inter data idle .midi().bits(0) // master inter data idle
.mssi().bits(0) // master SS idle .mssi().bits(0) // master SS idle
}); });
spi2.cr2.modify(|_, w| { spi2.cr2.modify(|_, w| w.tsize().bits(0));
w.tsize().bits(0) spi2.cr1.write(|w| w.spe().enabled());
}); spi2.cr1.modify(|_, w| w.cstart().started());
spi2.cr1.write(|w| w.spe().set_bit());
spi2.cr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 9)) });
} }
// DAC1 // DAC1
@ -423,7 +421,7 @@ fn spi4_setup(spi4: &stm32::SPI4) {
spi4.cfg1.modify(|_, w| { spi4.cfg1.modify(|_, w| {
w.mbr().bits(0) // clk/2 w.mbr().bits(0) // clk/2
.dsize().bits(16 - 1) .dsize().bits(16 - 1)
.fthvl().bits(1 - 1) // one data .fthvl().one_frame()
}); });
spi4.cfg2.modify(|_, w| unsafe { spi4.cfg2.modify(|_, w| unsafe {
w.afcntr().set_bit() w.afcntr().set_bit()
@ -444,8 +442,8 @@ fn spi4_setup(spi4: &stm32::SPI4) {
spi4.cr2.modify(|_, w| { spi4.cr2.modify(|_, w| {
w.tsize().bits(0) w.tsize().bits(0)
}); });
spi4.cr1.write(|w| w.spe().set_bit()); spi4.cr1.write(|w| w.spe().enabled());
spi4.cr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 9)) }); spi4.cr1.modify(|_, w| w.cstart().started());
} }
fn tim2_setup(tim2: &stm32::TIM2) { fn tim2_setup(tim2: &stm32::TIM2) {
@ -506,17 +504,16 @@ fn dma1_setup(dma1: &stm32::DMA1, dmamux1: &stm32::DMAMUX1, ma: usize, pa0: usiz
dma1.s1cr.modify(|_, w| w.en().set_bit()); dma1.s1cr.modify(|_, w| w.en().set_bit());
} }
static SPIP: Mutex<RefCell<Option<( type SpiPs = Option<(stm32::SPI1, stm32::SPI2, stm32::SPI4, stm32::SPI5)>;
stm32::SPI1, stm32::SPI2, stm32::SPI4, stm32::SPI5)>>> = static SPIP: Mutex<RefCell<SpiPs>> = Mutex::new(RefCell::new(None));
Mutex::new(RefCell::new(None));
#[link_section = ".sram1.datspi"] #[link_section = ".sram1.datspi"]
static mut DAT: u32 = (1 << 9) | (1 << 0); static mut DAT: u32 = 0x201; // EN | CSTART
static TIME: Mutex<RefCell<i64>> = Mutex::new(RefCell::new(0)); static TIME: Mutex<RefCell<i64>> = Mutex::new(RefCell::new(0));
#[link_section = ".sram3.eth"] #[link_section = ".sram3.eth"]
static mut ETH: eth::Device = eth::Device::new(); static mut ETHERNET: eth::Device = eth::Device::new();
const TCP_RX_BUFFER_SIZE: usize = 4096; const TCP_RX_BUFFER_SIZE: usize = 4096;
const TCP_TX_BUFFER_SIZE: usize = 4096; const TCP_TX_BUFFER_SIZE: usize = 4096;
@ -599,7 +596,8 @@ fn main() -> ! {
.sram3en().set_bit() .sram3en().set_bit()
); );
rcc.ahb1enr.modify(|_, w| w.dma1en().set_bit()); rcc.ahb1enr.modify(|_, w| w.dma1en().set_bit());
unsafe { DAT = (1 << 9) | (1 << 0) }; // init SRAM1 rodata can't load with sram1 disabled // init SRAM1 rodata can't load with sram1 disabled
unsafe { DAT = 0x201 }; // EN | CSTART
cortex_m::asm::dsb(); cortex_m::asm::dsb();
let dat_addr = unsafe { &DAT as *const _ } as usize; let dat_addr = unsafe { &DAT as *const _ } as usize;
cp.SCB.clean_dcache_by_address(dat_addr, 4); cp.SCB.clean_dcache_by_address(dat_addr, 4);
@ -628,7 +626,7 @@ fn main() -> ! {
eth::setup(&rcc, &dp.SYSCFG); eth::setup(&rcc, &dp.SYSCFG);
eth::setup_pins(&dp.GPIOA, &dp.GPIOB, &dp.GPIOC, &dp.GPIOG); eth::setup_pins(&dp.GPIOA, &dp.GPIOB, &dp.GPIOC, &dp.GPIOG);
let device = unsafe { &mut ETH }; let device = unsafe { &mut ETHERNET };
let hardware_addr = net::wire::EthernetAddress([0x10, 0xE2, 0xD5, 0x00, 0x03, 0x00]); let hardware_addr = net::wire::EthernetAddress([0x10, 0xE2, 0xD5, 0x00, 0x03, 0x00]);
unsafe { device.init(hardware_addr) }; unsafe { device.init(hardware_addr) };
let mut neighbor_cache_storage = [None; 8]; let mut neighbor_cache_storage = [None; 8];
@ -644,7 +642,7 @@ fn main() -> ! {
let mut sockets = net::socket::SocketSet::new(&mut socket_set_entries[..]); let mut sockets = net::socket::SocketSet::new(&mut socket_set_entries[..]);
create_socket!(sockets, tcp_rx_storage0, tcp_tx_storage0, tcp_handle0); create_socket!(sockets, tcp_rx_storage0, tcp_tx_storage0, tcp_handle0);
eth::enable_interrupt(&dp.ETHERNET_DMA); unsafe { eth::enable_interrupt(); }
unsafe { cp.NVIC.set_priority(stm32::Interrupt::ETH, 196); } // mid prio unsafe { cp.NVIC.set_priority(stm32::Interrupt::ETH, 196); } // mid prio
cp.NVIC.enable(stm32::Interrupt::ETH); cp.NVIC.enable(stm32::Interrupt::ETH);
@ -659,26 +657,24 @@ fn main() -> ! {
let mut last = 0; let mut last = 0;
loop { loop {
let time = cortex_m::interrupt::free(|cs| *TIME.borrow(cs).borrow()); let time = cortex_m::interrupt::free(|cs| *TIME.borrow(cs).borrow());
{ {
let socket = &mut *sockets.get::<net::socket::TcpSocket>(tcp_handle0); let socket = &mut *sockets.get::<net::socket::TcpSocket>(tcp_handle0);
if !socket.is_open() { if !(socket.is_open() || socket.is_listening()) {
socket.listen(80).unwrap_or_else(|e| warn!("TCP listen error: {:?}", e)); socket.listen(80).unwrap_or_else(|e| warn!("TCP listen error: {:?}", e));
} } else if last != time && socket.can_send() {
if socket.can_send() && last != time {
last = time; last = time;
let (x0, y0, x1, y1) = unsafe { let (x0, y0, x1, y1) = unsafe {
(IIR_STATE[0][0], IIR_STATE[0][2], IIR_STATE[1][0], IIR_STATE[1][2]) }; (IIR_STATE[0][0], IIR_STATE[0][2], IIR_STATE[1][0], IIR_STATE[1][2]) };
write!(socket, "t={} x0={:.1} y0={:.1} x1={:.1} y1={:.1}\n", time, x0, y0, x1, y1) writeln!(socket, "t={} x0={:.1} y0={:.1} x1={:.1} y1={:.1}",
time, x0, y0, x1, y1)
.unwrap_or_else(|e| warn!("TCP send error: {:?}", e)); .unwrap_or_else(|e| warn!("TCP send error: {:?}", e));
} }
} }
match iface.poll(&mut sockets, net::time::Instant::from_millis(time)) { match iface.poll(&mut sockets, net::time::Instant::from_millis(time)) {
Ok(_) => (), Ok(_) => (),
Err(net::Error::Unrecognized) => (),
Err(e) => info!("iface poll error: {:?}", e) Err(e) => info!("iface poll error: {:?}", e)
} }
cortex_m::asm::wfi(); cortex_m::asm::wfi();
} }
} }
@ -689,7 +685,8 @@ static mut IIR_CH: [IIR; 2] = [
IIR{ ba: [0., 0., 0., 0., 0.], y_offset: 0., IIR{ ba: [0., 0., 0., 0., 0.], y_offset: 0.,
y_min: -SCALE, y_max: SCALE }; 2]; y_min: -SCALE, y_max: SCALE }; 2];
#[link_section = ".data.spi1"] // seems to slow it down
// #[link_section = ".data.spi1"]
#[interrupt] #[interrupt]
fn SPI1() { fn SPI1() {
#[cfg(feature = "bkpt")] #[cfg(feature = "bkpt")]
@ -705,7 +702,7 @@ fn SPI1() {
if sr.rxp().bit_is_set() { if sr.rxp().bit_is_set() {
let rxdr = &spi1.rxdr as *const _ as *const u16; let rxdr = &spi1.rxdr as *const _ as *const u16;
let a = unsafe { ptr::read_volatile(rxdr) }; let a = unsafe { ptr::read_volatile(rxdr) };
let x0 = a as i16 as f32; let x0 = f32::from(a as i16);
let y0 = unsafe { IIR_CH[0].update(&mut IIR_STATE[0], x0) }; let y0 = unsafe { IIR_CH[0].update(&mut IIR_STATE[0], x0) };
let d = y0 as i16 as u16 ^ 0x8000; let d = y0 as i16 as u16 ^ 0x8000;
let txdr = &spi2.txdr as *const _ as *mut u16; let txdr = &spi2.txdr as *const _ as *mut u16;
@ -719,7 +716,7 @@ fn SPI1() {
if sr.rxp().bit_is_set() { if sr.rxp().bit_is_set() {
let rxdr = &spi5.rxdr as *const _ as *const u16; let rxdr = &spi5.rxdr as *const _ as *const u16;
let a = unsafe { ptr::read_volatile(rxdr) }; let a = unsafe { ptr::read_volatile(rxdr) };
let x0 = a as i16 as f32; let x0 = f32::from(a as i16);
let y0 = unsafe { IIR_CH[1].update(&mut IIR_STATE[1], x0) }; let y0 = unsafe { IIR_CH[1].update(&mut IIR_STATE[1], x0) };
let d = y0 as i16 as u16 ^ 0x8000; let d = y0 as i16 as u16 ^ 0x8000;
let txdr = &spi4.txdr as *const _ as *mut u16; let txdr = &spi4.txdr as *const _ as *mut u16;
@ -732,8 +729,7 @@ fn SPI1() {
#[interrupt] #[interrupt]
fn ETH() { fn ETH() {
let p = unsafe { Peripherals::steal() }; unsafe { eth::interrupt_handler() }
eth::eth_interrupt_handler(&p.ETHERNET_DMA);
} }
#[exception] #[exception]