From 9863ba3a3390643babd6285776e78850901da878 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Sun, 28 Apr 2019 20:44:38 +0200 Subject: [PATCH] cleanup --- src/eth.rs | 52 ++++++++++++++++++++++++----------------------- src/main.rs | 58 +++++++++++++++++++++++++---------------------------- 2 files changed, 54 insertions(+), 56 deletions(-) diff --git a/src/eth.rs b/src/eth.rs index aebc3c0..2229e50 100644 --- a/src/eth.rs +++ b/src/eth.rs @@ -21,7 +21,7 @@ mod phy_consts { pub const PHY_REG_CTL: u8 = 0x0D; // Ethernet PHY Register Control pub const PHY_REG_ADDAR: u8 = 0x0E; // Ethernet PHY Address or Data - pub const PHY_REG_WUCSR: u16 = 08010; + pub const PHY_REG_WUCSR: u16 = 0x8010; pub const PHY_REG_BCR_COLTEST: u16 = 1 << 7; pub const PHY_REG_BCR_FD: u16 = 1 << 8; @@ -47,25 +47,25 @@ mod phy_consts { } use self::phy_consts::*; -pub const MTU: usize = 1522; +pub const MTU: usize = 1536; -const EMAC_DES3_OWN: u32 = 0x80000000; -const EMAC_DES3_CTXT: u32 = 0x40000000; -const EMAC_DES3_FD: u32 = 0x20000000; -const EMAC_DES3_LD: u32 = 0x10000000; -const EMAC_DES3_ES: u32 = 0x00008000; -const EMAC_TDES2_IOC: u32 = 0x80000000; -const EMAC_RDES3_IOC: u32 = 0x40000000; -const EMAC_RDES3_PL: u32 = 0x00007FFF; -const EMAC_RDES3_BUF1V: u32 = 0x01000000; -const EMAC_TDES2_B1L: u32 = 0x00003FFF; -const EMAC_DES0_BUF1AP: u32 = 0xFFFFFFFF; +const EMAC_DES3_OWN: u32 = 0x8000_0000; +const EMAC_DES3_CTXT: u32 = 0x4000_0000; +const EMAC_DES3_FD: u32 = 0x2000_0000; +const EMAC_DES3_LD: u32 = 0x1000_0000; +const EMAC_DES3_ES: u32 = 0x0000_8000; +const EMAC_TDES2_IOC: u32 = 0x8000_0000; +const EMAC_RDES3_IOC: u32 = 0x4000_0000; +const EMAC_RDES3_PL: u32 = 0x0000_7FFF; +const EMAC_RDES3_BUF1V: u32 = 0x0100_0000; +const EMAC_TDES2_B1L: u32 = 0x0000_3FFF; +const EMAC_DES0_BUF1AP: u32 = 0xFFFF_FFFF; const ETH_DESC_U32_SIZE: usize = 4; const ETH_TX_BUFFER_COUNT: usize = 4; -const ETH_TX_BUFFER_SIZE: usize = 1536; +const ETH_TX_BUFFER_SIZE: usize = MTU; const ETH_RX_BUFFER_COUNT: usize = 4; -const ETH_RX_BUFFER_SIZE: usize = 1536; +const ETH_RX_BUFFER_SIZE: usize = MTU; #[allow(dead_code)] mod cr_consts { @@ -403,14 +403,14 @@ impl Device { }); // Set the MAC address eth_mac.maca0lr.write(|w| - w.addrlo().bits( mac.0[0] as u32 | - ((mac.0[1] as u32) << 8) | - ((mac.0[2] as u32) << 16) | - ((mac.0[3] as u32) << 24)) + w.addrlo().bits( u32::from(mac.0[0]) | + (u32::from(mac.0[1]) << 8) | + (u32::from(mac.0[2]) << 16) | + (u32::from(mac.0[3]) << 24)) ); eth_mac.maca0hr.write(|w| - w.addrhi().bits( mac.0[4] as u16 | - ((mac.0[5] as u16) << 8)) + w.addrhi().bits( u16::from(mac.0[4]) | + (u16::from(mac.0[5]) << 8)) .ae().set_bit() //.sa().clear_bit() //.mbc().bits(0b000000) @@ -543,7 +543,7 @@ impl<'a, 'b> phy::Device<'a> for &'b mut Device { fn capabilities(&self) -> phy::DeviceCapabilities { let mut capabilities = phy::DeviceCapabilities::default(); - capabilities.max_transmission_unit = 1500; + capabilities.max_transmission_unit = 1514; capabilities.max_burst_size = Some(self.tx.desc_buf.len()); capabilities } @@ -592,7 +592,8 @@ impl<'a> phy::TxToken for TxToken<'a> { } } -pub fn eth_interrupt_handler(eth_dma: &stm32::ETHERNET_DMA) { +pub unsafe fn interrupt_handler() { + let eth_dma = &*stm32::ETHERNET_DMA::ptr(); eth_dma.dmacsr.write(|w| w .nis().set_bit() @@ -601,8 +602,9 @@ pub fn eth_interrupt_handler(eth_dma: &stm32::ETHERNET_DMA) { ); } -pub fn enable_interrupt(dma: &stm32::ETHERNET_DMA) { - dma.dmacier.modify(|_, w| +pub unsafe fn enable_interrupt() { + let eth_dma = &*stm32::ETHERNET_DMA::ptr(); + eth_dma.dmacier.modify(|_, w| w .nie().set_bit() .rie().set_bit() diff --git a/src/main.rs b/src/main.rs index 87eca96..55ae625 100644 --- a/src/main.rs +++ b/src/main.rs @@ -335,7 +335,7 @@ fn spi1_setup(spi1: &stm32::SPI1) { spi1.cfg1.modify(|_, w| { w.mbr().bits(1) // clk/4 .dsize().bits(16 - 1) - .fthvl().bits(1 - 1) // one data + .fthvl().one_frame() }); spi1.cfg2.modify(|_, w| unsafe { w.afcntr().set_bit() @@ -364,7 +364,7 @@ fn spi5_setup(spi5: &stm32::SPI5) { spi5.cfg1.modify(|_, w| { w.mbr().bits(1) // clk/4 .dsize().bits(16 - 1) - .fthvl().bits(1 - 1) // one data + .fthvl().one_frame() }); spi5.cfg2.modify(|_, w| unsafe { w.afcntr().set_bit() @@ -393,7 +393,7 @@ fn spi2_setup(spi2: &stm32::SPI2) { spi2.cfg1.modify(|_, w| { w.mbr().bits(0) // clk/2 .dsize().bits(16 - 1) - .fthvl().bits(1 - 1) // one data + .fthvl().one_frame() }); spi2.cfg2.modify(|_, w| unsafe { w.afcntr().set_bit() @@ -411,11 +411,9 @@ fn spi2_setup(spi2: &stm32::SPI2) { .midi().bits(0) // master inter data idle .mssi().bits(0) // master SS idle }); - spi2.cr2.modify(|_, w| { - w.tsize().bits(0) - }); - spi2.cr1.write(|w| w.spe().set_bit()); - spi2.cr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 9)) }); + spi2.cr2.modify(|_, w| w.tsize().bits(0)); + spi2.cr1.write(|w| w.spe().enabled()); + spi2.cr1.modify(|_, w| w.cstart().started()); } // DAC1 @@ -423,7 +421,7 @@ fn spi4_setup(spi4: &stm32::SPI4) { spi4.cfg1.modify(|_, w| { w.mbr().bits(0) // clk/2 .dsize().bits(16 - 1) - .fthvl().bits(1 - 1) // one data + .fthvl().one_frame() }); spi4.cfg2.modify(|_, w| unsafe { w.afcntr().set_bit() @@ -444,8 +442,8 @@ fn spi4_setup(spi4: &stm32::SPI4) { spi4.cr2.modify(|_, w| { w.tsize().bits(0) }); - spi4.cr1.write(|w| w.spe().set_bit()); - spi4.cr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 9)) }); + spi4.cr1.write(|w| w.spe().enabled()); + spi4.cr1.modify(|_, w| w.cstart().started()); } fn tim2_setup(tim2: &stm32::TIM2) { @@ -506,17 +504,16 @@ fn dma1_setup(dma1: &stm32::DMA1, dmamux1: &stm32::DMAMUX1, ma: usize, pa0: usiz dma1.s1cr.modify(|_, w| w.en().set_bit()); } -static SPIP: Mutex>> = - Mutex::new(RefCell::new(None)); +type SpiPs = Option<(stm32::SPI1, stm32::SPI2, stm32::SPI4, stm32::SPI5)>; +static SPIP: Mutex> = Mutex::new(RefCell::new(None)); #[link_section = ".sram1.datspi"] -static mut DAT: u32 = (1 << 9) | (1 << 0); +static mut DAT: u32 = 0x201; // EN | CSTART static TIME: Mutex> = Mutex::new(RefCell::new(0)); #[link_section = ".sram3.eth"] -static mut ETH: eth::Device = eth::Device::new(); +static mut ETHERNET: eth::Device = eth::Device::new(); const TCP_RX_BUFFER_SIZE: usize = 4096; const TCP_TX_BUFFER_SIZE: usize = 4096; @@ -599,7 +596,8 @@ fn main() -> ! { .sram3en().set_bit() ); rcc.ahb1enr.modify(|_, w| w.dma1en().set_bit()); - unsafe { DAT = (1 << 9) | (1 << 0) }; // init SRAM1 rodata can't load with sram1 disabled + // init SRAM1 rodata can't load with sram1 disabled + unsafe { DAT = 0x201 }; // EN | CSTART cortex_m::asm::dsb(); let dat_addr = unsafe { &DAT as *const _ } as usize; cp.SCB.clean_dcache_by_address(dat_addr, 4); @@ -628,7 +626,7 @@ fn main() -> ! { eth::setup(&rcc, &dp.SYSCFG); eth::setup_pins(&dp.GPIOA, &dp.GPIOB, &dp.GPIOC, &dp.GPIOG); - let device = unsafe { &mut ETH }; + let device = unsafe { &mut ETHERNET }; let hardware_addr = net::wire::EthernetAddress([0x10, 0xE2, 0xD5, 0x00, 0x03, 0x00]); unsafe { device.init(hardware_addr) }; let mut neighbor_cache_storage = [None; 8]; @@ -644,7 +642,7 @@ fn main() -> ! { let mut sockets = net::socket::SocketSet::new(&mut socket_set_entries[..]); create_socket!(sockets, tcp_rx_storage0, tcp_tx_storage0, tcp_handle0); - eth::enable_interrupt(&dp.ETHERNET_DMA); + unsafe { eth::enable_interrupt(); } unsafe { cp.NVIC.set_priority(stm32::Interrupt::ETH, 196); } // mid prio cp.NVIC.enable(stm32::Interrupt::ETH); @@ -659,26 +657,24 @@ fn main() -> ! { let mut last = 0; loop { let time = cortex_m::interrupt::free(|cs| *TIME.borrow(cs).borrow()); - { let socket = &mut *sockets.get::(tcp_handle0); - if !socket.is_open() { + if !(socket.is_open() || socket.is_listening()) { socket.listen(80).unwrap_or_else(|e| warn!("TCP listen error: {:?}", e)); - } - if socket.can_send() && last != time { + } else if last != time && socket.can_send() { last = time; let (x0, y0, x1, y1) = unsafe { (IIR_STATE[0][0], IIR_STATE[0][2], IIR_STATE[1][0], IIR_STATE[1][2]) }; - write!(socket, "t={} x0={:.1} y0={:.1} x1={:.1} y1={:.1}\n", time, x0, y0, x1, y1) + writeln!(socket, "t={} x0={:.1} y0={:.1} x1={:.1} y1={:.1}", + time, x0, y0, x1, y1) .unwrap_or_else(|e| warn!("TCP send error: {:?}", e)); } } - match iface.poll(&mut sockets, net::time::Instant::from_millis(time)) { Ok(_) => (), + Err(net::Error::Unrecognized) => (), Err(e) => info!("iface poll error: {:?}", e) } - cortex_m::asm::wfi(); } } @@ -689,7 +685,8 @@ static mut IIR_CH: [IIR; 2] = [ IIR{ ba: [0., 0., 0., 0., 0.], y_offset: 0., y_min: -SCALE, y_max: SCALE }; 2]; -#[link_section = ".data.spi1"] +// seems to slow it down +// #[link_section = ".data.spi1"] #[interrupt] fn SPI1() { #[cfg(feature = "bkpt")] @@ -705,7 +702,7 @@ fn SPI1() { if sr.rxp().bit_is_set() { let rxdr = &spi1.rxdr as *const _ as *const u16; let a = unsafe { ptr::read_volatile(rxdr) }; - let x0 = a as i16 as f32; + let x0 = f32::from(a as i16); let y0 = unsafe { IIR_CH[0].update(&mut IIR_STATE[0], x0) }; let d = y0 as i16 as u16 ^ 0x8000; let txdr = &spi2.txdr as *const _ as *mut u16; @@ -719,7 +716,7 @@ fn SPI1() { if sr.rxp().bit_is_set() { let rxdr = &spi5.rxdr as *const _ as *const u16; let a = unsafe { ptr::read_volatile(rxdr) }; - let x0 = a as i16 as f32; + let x0 = f32::from(a as i16); let y0 = unsafe { IIR_CH[1].update(&mut IIR_STATE[1], x0) }; let d = y0 as i16 as u16 ^ 0x8000; let txdr = &spi4.txdr as *const _ as *mut u16; @@ -732,8 +729,7 @@ fn SPI1() { #[interrupt] fn ETH() { - let p = unsafe { Peripherals::steal() }; - eth::eth_interrupt_handler(&p.ETHERNET_DMA); + unsafe { eth::interrupt_handler() } } #[exception]