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lockin: merge sample_phase/frequency computation

This commit is contained in:
Robert Jördens 2021-05-06 16:22:42 +02:00
parent 4780a97528
commit 97cca486b5
1 changed files with 23 additions and 33 deletions
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54
src/bin/lockin.rs
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@ -29,7 +29,7 @@ const DAC_SEQUENCE: [i16; design_parameters::SAMPLE_BUFFER_SIZE] =
enum Conf { enum Conf {
Magnitude, Magnitude,
Phase, Phase,
PllFrequency, ReferenceFrequency,
LogPower, LogPower,
InPhase, InPhase,
Quadrature, Quadrature,
@ -165,50 +165,38 @@ const APP: () = {
let lockin = c.resources.lockin; let lockin = c.resources.lockin;
let settings = c.resources.settings; let settings = c.resources.settings;
let mut pll_frequency = 0; let (reference_phase, reference_frequency) = match settings.lockin_mode
{
let (sample_phase, sample_frequency) = match settings.lockin_mode {
LockinMode::External => { LockinMode::External => {
let timestamp = let timestamp =
c.resources.timestamper.latest_timestamp().unwrap_or(None); // Ignore data from timer capture overflows. c.resources.timestamper.latest_timestamp().unwrap_or(None); // Ignore data from timer capture overflows.
let (pll_phase, frequency) = c.resources.pll.update( let (pll_phase, pll_frequency) = c.resources.pll.update(
timestamp.map(|t| t as i32), timestamp.map(|t| t as i32),
settings.pll_tc[0], settings.pll_tc[0],
settings.pll_tc[1], settings.pll_tc[1],
); );
(
pll_frequency = frequency; pll_phase,
(pll_frequency
let sample_frequency = ((pll_frequency
>> design_parameters::SAMPLE_BUFFER_SIZE_LOG2) >> design_parameters::SAMPLE_BUFFER_SIZE_LOG2)
as i32) as i32,
.wrapping_mul(settings.lockin_harmonic); )
let sample_phase = settings.lockin_phase.wrapping_add(
pll_phase.wrapping_mul(settings.lockin_harmonic),
);
(sample_phase, sample_frequency)
} }
LockinMode::Internal => { LockinMode::Internal => {
// Reference phase and frequency are known. // Reference phase and frequency are known.
let pll_phase = 0i32; (
let pll_frequency = 1i32 << 30,
1i32 << (32 - design_parameters::SAMPLE_BUFFER_SIZE_LOG2); 1i32 << (32 - design_parameters::SAMPLE_BUFFER_SIZE_LOG2),
)
// Demodulation LO phase offset
let phase_offset: i32 = 1 << 30;
let sample_frequency = (pll_frequency as i32)
.wrapping_mul(settings.lockin_harmonic);
let sample_phase = phase_offset.wrapping_add(
pll_phase.wrapping_mul(settings.lockin_harmonic),
);
(sample_phase, sample_frequency)
} }
}; };
let sample_frequency =
reference_frequency.wrapping_mul(settings.lockin_harmonic);
let sample_phase = settings.lockin_phase.wrapping_add(
reference_phase.wrapping_mul(settings.lockin_harmonic),
);
let output: Complex<i32> = adc_samples[0] let output: Complex<i32> = adc_samples[0]
.iter() .iter()
// Zip in the LO phase. // Zip in the LO phase.
@ -230,7 +218,9 @@ const APP: () = {
Conf::Magnitude => output.abs_sqr() as i32 >> 16, Conf::Magnitude => output.abs_sqr() as i32 >> 16,
Conf::Phase => output.arg() >> 16, Conf::Phase => output.arg() >> 16,
Conf::LogPower => (output.log2() << 24) as i32 >> 16, Conf::LogPower => (output.log2() << 24) as i32 >> 16,
Conf::PllFrequency => pll_frequency as i32 >> 16, Conf::ReferenceFrequency => {
reference_frequency as i32 >> 16
}
Conf::InPhase => output.re >> 16, Conf::InPhase => output.re >> 16,
Conf::Quadrature => output.im >> 16, Conf::Quadrature => output.im >> 16,
Conf::Modulation => DAC_SEQUENCE[i] as i32, Conf::Modulation => DAC_SEQUENCE[i] as i32,