From 9569df9e820028692887fc1e2315372e33d9cec3 Mon Sep 17 00:00:00 2001
From: Ryan Summers <ryan.summers@vertigo-designs.com>
Date: Thu, 6 May 2021 14:34:09 +0200
Subject: [PATCH] Renaming power -> magnitude

---
 src/bin/lockin.rs | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/bin/lockin.rs b/src/bin/lockin.rs
index ce60048..6212a7e 100644
--- a/src/bin/lockin.rs
+++ b/src/bin/lockin.rs
@@ -27,7 +27,7 @@ const DAC_SEQUENCE: [i16; design_parameters::SAMPLE_BUFFER_SIZE] =
 
 #[derive(Copy, Clone, Debug, Deserialize, Miniconf)]
 enum Conf {
-    Power,
+    Magnitude,
     Phase,
     PllFrequency,
     LogPower,
@@ -227,7 +227,7 @@ const APP: () = {
         for (channel, samples) in dac_samples.iter_mut().enumerate() {
             for (i, sample) in samples.iter_mut().enumerate() {
                 let value = match settings.output_conf[channel] {
-                    Conf::Power => output.abs_sqr() as i32 >> 16,
+                    Conf::Magnitude => output.abs_sqr() as i32 >> 16,
                     Conf::Phase => output.arg() >> 16,
                     Conf::LogPower => (output.log2() << 24) as i32 >> 16,
                     Conf::PllFrequency => pll_frequency as i32 >> 16,