diff --git a/src/adc.rs b/src/adc.rs
index f6b4506..3e60a0d 100644
--- a/src/adc.rs
+++ b/src/adc.rs
@@ -1,9 +1,13 @@
 ///! Stabilizer ADC management interface
 ///!
-///! The Stabilizer ADCs utilize a DMA channel to trigger sampling. The SPI streams are configured
-///! for full-duplex operation, but only RX is connected to physical pins. A timer channel is
-///! configured to generate a DMA write into the SPI TXFIFO, which initiates a SPI transfer and
-///! results in an ADC sample read for both channels.
+///! The Stabilizer ADCs utilize three DMA channels: one to trigger sampling, one to collect
+///! samples, and one to clear the TXTF flag betwen samples. The SPI interfaces are configured
+///! for receiver-only operation. A timer channel is
+///! configured to generate a DMA write into the SPI CR1 register, which initiates a SPI transfer and
+///! results in a single ADC sample read for both channels. A separate timer channel is configured to
+///! occur immediately before the trigger channel, which initiates a write to the IFCR (flag-clear)
+///! register to clear the TXTF flag, which allows for a new transmission to be generated by the
+///! trigger channel.
 ///!
 ///! In order to read multiple samples without interrupting the CPU, a separate DMA transfer is
 ///! configured to read from each of the ADC SPI RX FIFOs. Due to the design of the SPI peripheral,