From 8dd72ae75e915e8c3e8490fb6599bf4452838265 Mon Sep 17 00:00:00 2001
From: Ryan Summers <ryan.summers@vertigo-designs.com>
Date: Mon, 18 Jan 2021 16:52:09 +0100
Subject: [PATCH] Reordering

---
 src/hardware/adc.rs | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/src/hardware/adc.rs b/src/hardware/adc.rs
index e3b8e56..188e436 100644
--- a/src/hardware/adc.rs
+++ b/src/hardware/adc.rs
@@ -1,10 +1,3 @@
-use super::timers;
-use hal::dma::{
-    config::Priority,
-    dma::{DMAReq, DmaConfig},
-    traits::TargetAddress,
-    MemoryToPeripheral, PeripheralToMemory, Transfer,
-};
 ///! Stabilizer ADC management interface
 ///!
 ///! # Design
@@ -83,6 +76,14 @@ use stm32h7xx_hal as hal;
 
 use crate::SAMPLE_BUFFER_SIZE;
 
+use super::timers;
+use hal::dma::{
+    config::Priority,
+    dma::{DMAReq, DmaConfig},
+    traits::TargetAddress,
+    MemoryToPeripheral, PeripheralToMemory, Transfer,
+};
+
 // The following data is written by the timer ADC sample trigger into the SPI CR1 to start the
 // transfer. Data in AXI SRAM is not initialized on boot, so the contents are random. This value is
 // initialized during setup.