stm32h7 svd and pac changes
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61adbd8c9e
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16
src/eth.rs
16
src/eth.rs
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@ -360,7 +360,6 @@ impl Device {
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cortex_m::interrupt::free(|_cs| {
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let eth_mac = &*stm32::ETHERNET_MAC::ptr();
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let eth_dma = &*stm32::ETHERNET_DMA::ptr();
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let _eth_mmc = &*stm32::ETHERNET_MMC::ptr();
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let eth_mtl = &*stm32::ETHERNET_MTL::ptr();
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eth_dma.dmamr.modify(|_, w| w.swr().set_bit());
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@ -407,9 +406,6 @@ impl Device {
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eth_mac.maca0hr.write(|w|
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w.addrhi().bits( u16::from(mac.0[4]) |
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(u16::from(mac.0[5]) << 8))
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.ae().set_bit()
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//.sa().clear_bit()
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//.mbc().bits(0b000000)
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);
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// frame filter register
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eth_mac.macpfr.modify(|_, w| {
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@ -433,12 +429,12 @@ impl Device {
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});
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eth_mac.macwtr.write(|w| w.pwe().clear_bit());
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// Flow Control Register
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eth_mac.macqtxfcr.modify(|_, w| {
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eth_mac.macqtx_fcr.modify(|_, w| {
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// Pause time
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w.pt().bits(0x100)
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});
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eth_mac.macrxfcr.modify(|_, w| w);
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eth_mtl.mtlrxqomr.modify(|_, w|
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eth_mac.macrx_fcr.modify(|_, w| w);
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eth_mtl.mtlrx_qomr.modify(|_, w|
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w
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// Receive store and forward
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.rsf().set_bit()
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@ -449,7 +445,7 @@ impl Device {
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// Forward undersized good packets
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.fup().clear_bit()
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);
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eth_mtl.mtltxqomr.modify(|_, w| {
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eth_mtl.mtltx_qomr.modify(|_, w| {
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w
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// Transmit store and forward
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.tsf().set_bit()
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@ -473,7 +469,7 @@ impl Device {
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// operation mode register
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eth_dma.dmamr.modify(|_, w| {
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w
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.intm().clear_bit() // FIXME: bits(0b00)
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.intm().bits(0b00)
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// Rx Tx priority ratio 1:1
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.pr().bits(0b000)
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.txpr().clear_bit()
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@ -519,7 +515,7 @@ impl Device {
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w.re().bit(true) // Receiver Enable
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.te().bit(true) // Transmiter Enable
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});
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eth_mtl.mtltxqomr.modify(|_, w| w.ftq().set_bit());
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eth_mtl.mtltx_qomr.modify(|_, w| w.ftq().set_bit());
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// Manage DMA transmission and reception
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eth_dma.dmactx_cr.modify(|_, w| w.st().set_bit());
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@ -56,7 +56,7 @@ mod build_info {
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fn pwr_setup(pwr: &stm32::PWR) {
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// go to VOS1 voltage scale for high perf
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pwr.cr3.write(|w|
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w.sden().set_bit()
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w.scuen().set_bit()
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.ldoen().set_bit()
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.bypass().clear_bit()
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);
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