From 7fc6f5c4adfa3276ce92a40f3785130dda90d812 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Thu, 26 Nov 2020 16:24:42 +0100 Subject: [PATCH] clippy lints --- .github/workflows/ci.yml | 2 +- ad9959/src/lib.rs | 125 ++++++++++++++------------------------- src/adc.rs | 4 +- src/dac.rs | 4 +- src/main.rs | 16 +++-- src/pounder/mod.rs | 2 +- src/server.rs | 6 +- 7 files changed, 62 insertions(+), 97 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index c2498fc..1f131c8 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -17,7 +17,7 @@ jobs: - uses: actions-rs/toolchain@v1 with: profile: minimal - toolchain: stable + toolchain: nightly override: true components: rustfmt - name: cargo fmt --check diff --git a/ad9959/src/lib.rs b/ad9959/src/lib.rs index d12041c..0f6b237 100644 --- a/ad9959/src/lib.rs +++ b/ad9959/src/lib.rs @@ -127,30 +127,27 @@ where system_clock_multiplier: 1, }; - ad9959.io_update.set_low().or_else(|_| Err(Error::Pin))?; + ad9959.io_update.set_low().or(Err(Error::Pin))?; // Reset the AD9959 - reset_pin.set_high().or_else(|_| Err(Error::Pin))?; + reset_pin.set_high().or(Err(Error::Pin))?; // Delay for a clock cycle to allow the device to reset. ad9959 .delay .delay_ms((1000.0 / clock_frequency as f32) as u8); - reset_pin.set_low().or_else(|_| Err(Error::Pin))?; + reset_pin.set_low().or(Err(Error::Pin))?; ad9959 .interface .configure_mode(Mode::SingleBitTwoWire) - .map_err(|_| Error::Interface)?; + .or(Err(Error::Interface))?; // Program the interface configuration in the AD9959. Default to all channels enabled. let mut csr: [u8; 1] = [0xF0]; csr[0].set_bits(1..3, desired_mode as u8); - ad9959 - .interface - .write(Register::CSR as u8, &csr) - .map_err(|_| Error::Interface)?; + ad9959.write(Register::CSR, &csr)?; // Latch the configuration registers to make them active. ad9959.latch_configuration()?; @@ -158,14 +155,11 @@ where ad9959 .interface .configure_mode(desired_mode) - .map_err(|_| Error::Interface)?; + .or(Err(Error::Interface))?; // Read back the CSR to ensure it specifies the mode correctly. let mut updated_csr: [u8; 1] = [0]; - ad9959 - .interface - .read(Register::CSR as u8, &mut updated_csr) - .map_err(|_| Error::Interface)?; + ad9959.read(Register::CSR, &mut updated_csr)?; if updated_csr[0] != csr[0] { return Err(Error::Check); } @@ -175,14 +169,26 @@ where Ok(ad9959) } + fn read(&mut self, reg: Register, data: &mut [u8]) -> Result<(), Error> { + self.interface + .read(reg as u8, data) + .or(Err(Error::Interface)) + } + + fn write(&mut self, reg: Register, data: &[u8]) -> Result<(), Error> { + self.interface + .write(reg as u8, data) + .or(Err(Error::Interface)) + } + /// Latch the DDS configuration to ensure it is active on the output channels. fn latch_configuration(&mut self) -> Result<(), Error> { - self.io_update.set_high().or_else(|_| Err(Error::Pin))?; + self.io_update.set_high().or(Err(Error::Pin))?; // The SYNC_CLK is 1/4 the system clock frequency. The IO_UPDATE pin must be latched for one // full SYNC_CLK pulse to register. For safety, we latch for 5 here. self.delay .delay_ms((5000.0 / self.system_clock_frequency()) as u8); - self.io_update.set_low().or_else(|_| Err(Error::Pin))?; + self.io_update.set_low().or(Err(Error::Pin))?; Ok(()) } @@ -214,17 +220,13 @@ where // TODO: Update / disable any enabled channels? let mut fr1: [u8; 3] = [0, 0, 0]; - self.interface - .read(Register::FR1 as u8, &mut fr1) - .map_err(|_| Error::Interface)?; + self.read(Register::FR1, &mut fr1)?; fr1[0].set_bits(2..=6, multiplier); let vco_range = frequency > 255e6; fr1[0].set_bit(7, vco_range); - self.interface - .write(Register::FR1 as u8, &fr1) - .map_err(|_| Error::Interface)?; + self.write(Register::FR1, &fr1)?; self.system_clock_multiplier = multiplier; Ok(self.system_clock_frequency()) @@ -238,9 +240,7 @@ where /// Get the current reference clock multiplier. pub fn get_reference_clock_multiplier(&mut self) -> Result { let mut fr1: [u8; 3] = [0, 0, 0]; - self.interface - .read(Register::FR1 as u8, &mut fr1) - .map_err(|_| Error::Interface)?; + self.read(Register::FR1, &mut fr1)?; Ok(fr1[0].get_bits(2..=6) as u8) } @@ -254,46 +254,34 @@ where /// True if the self test succeeded. False otherwise. pub fn self_test(&mut self) -> Result { let mut csr: [u8; 1] = [0]; - self.interface - .read(Register::CSR as u8, &mut csr) - .map_err(|_| Error::Interface)?; + self.read(Register::CSR, &mut csr)?; let old_csr = csr[0]; // Enable all channels. csr[0].set_bits(4..8, 0xF); - self.interface - .write(Register::CSR as u8, &csr) - .map_err(|_| Error::Interface)?; + self.write(Register::CSR, &csr)?; // Read back the enable. csr[0] = 0; - self.interface - .read(Register::CSR as u8, &mut csr) - .map_err(|_| Error::Interface)?; + self.read(Register::CSR, &mut csr)?; if csr[0].get_bits(4..8) != 0xF { return Ok(false); } // Clear all channel enables. csr[0].set_bits(4..8, 0x0); - self.interface - .write(Register::CSR as u8, &csr) - .map_err(|_| Error::Interface)?; + self.write(Register::CSR, &csr)?; // Read back the enable. csr[0] = 0xFF; - self.interface - .read(Register::CSR as u8, &mut csr) - .map_err(|_| Error::Interface)?; + self.read(Register::CSR, &mut csr)?; if csr[0].get_bits(4..8) != 0 { return Ok(false); } // Restore the CSR. csr[0] = old_csr; - self.interface - .write(Register::CSR as u8, &csr) - .map_err(|_| Error::Interface)?; + self.write(Register::CSR, &csr)?; Ok(true) } @@ -307,13 +295,9 @@ where /// Enable an output channel. pub fn enable_channel(&mut self, channel: Channel) -> Result<(), Error> { let mut csr: [u8; 1] = [0]; - self.interface - .read(Register::CSR as u8, &mut csr) - .map_err(|_| Error::Interface)?; + self.read(Register::CSR, &mut csr)?; csr[0].set_bit(channel as usize + 4, true); - self.interface - .write(Register::CSR as u8, &csr) - .map_err(|_| Error::Interface)?; + self.write(Register::CSR, &csr)?; Ok(()) } @@ -321,13 +305,9 @@ where /// Disable an output channel. pub fn disable_channel(&mut self, channel: Channel) -> Result<(), Error> { let mut csr: [u8; 1] = [0]; - self.interface - .read(Register::CSR as u8, &mut csr) - .map_err(|_| Error::Interface)?; + self.read(Register::CSR, &mut csr)?; csr[0].set_bit(channel as usize + 4, false); - self.interface - .write(Register::CSR as u8, &csr) - .map_err(|_| Error::Interface)?; + self.write(Register::CSR, &csr)?; Ok(()) } @@ -335,9 +315,7 @@ where /// Determine if an output channel is enabled. pub fn is_enabled(&mut self, channel: Channel) -> Result { let mut csr: [u8; 1] = [0; 1]; - self.interface - .read(Register::CSR as u8, &mut csr) - .map_err(|_| Error::Interface)?; + self.read(Register::CSR, &mut csr)?; Ok(csr[0].get_bit(channel as usize + 4)) } @@ -357,28 +335,20 @@ where // Disable all other outputs so that we can update the configuration register of only the // specified channel. let mut csr: [u8; 1] = [0]; - self.interface - .read(Register::CSR as u8, &mut csr) - .map_err(|_| Error::Interface)?; + self.read(Register::CSR, &mut csr)?; let mut new_csr = csr; new_csr[0].set_bits(4..8, 0); new_csr[0].set_bit(4 + channel as usize, true); - self.interface - .write(Register::CSR as u8, &new_csr) - .map_err(|_| Error::Interface)?; + self.write(Register::CSR, &new_csr)?; - self.interface - .write(register as u8, &data) - .map_err(|_| Error::Interface)?; + self.write(register, &data)?; // Latch the configuration and restore the previous CSR. Note that the re-enable of the // channel happens immediately, so the CSR update does not need to be latched. self.latch_configuration()?; - self.interface - .write(Register::CSR as u8, &csr) - .map_err(|_| Error::Interface)?; + self.write(Register::CSR, &csr)?; Ok(()) } @@ -398,27 +368,18 @@ where // Disable all other channels in the CSR so that we can read the configuration register of // only the desired channel. let mut csr: [u8; 1] = [0]; - self.interface - .read(Register::CSR as u8, &mut csr) - .map_err(|_| Error::Interface)?; + self.read(Register::CSR, &mut csr)?; let mut new_csr = csr; new_csr[0].set_bits(4..8, 0); new_csr[0].set_bit(4 + channel as usize, true); - self.interface - .write(Register::CSR as u8, &new_csr) - .map_err(|_| Error::Interface)?; - - self.interface - .read(register as u8, &mut data) - .map_err(|_| Error::Interface)?; + self.write(Register::CSR, &new_csr)?; + self.read(register, &mut data)?; // Restore the previous CSR. Note that the re-enable of the channel happens immediately, so // the CSR update does not need to be latched. - self.interface - .write(Register::CSR as u8, &csr) - .map_err(|_| Error::Interface)?; + self.write(Register::CSR, &csr)?; Ok(()) } diff --git a/src/adc.rs b/src/adc.rs index 9d344dc..87702b0 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -244,7 +244,7 @@ impl Adc0Input { // Wait for the transfer to fully complete before continuing. // Note: If a device hangs up, check that this conditional is passing correctly, as there is // no time-out checks here in the interest of execution speed. - while self.transfer.get_transfer_complete_flag() == false {} + while !self.transfer.get_transfer_complete_flag() {} // Start the next transfer. self.transfer.clear_interrupts(); @@ -371,7 +371,7 @@ impl Adc1Input { // Wait for the transfer to fully complete before continuing. // Note: If a device hangs up, check that this conditional is passing correctly, as there is // no time-out checks here in the interest of execution speed. - while self.transfer.get_transfer_complete_flag() == false {} + while !self.transfer.get_transfer_complete_flag() {} // Start the next transfer. self.transfer.clear_interrupts(); diff --git a/src/dac.rs b/src/dac.rs index d6325c2..ef1e267 100644 --- a/src/dac.rs +++ b/src/dac.rs @@ -207,7 +207,7 @@ impl Dac0Output { } else { // Note: If a device hangs up, check that this conditional is passing correctly, as // there is no time-out checks here in the interest of execution speed. - while self.transfer.get_transfer_complete_flag() == false {} + while !self.transfer.get_transfer_complete_flag() {} } // Start the next transfer. @@ -303,7 +303,7 @@ impl Dac1Output { } else { // Note: If a device hangs up, check that this conditional is passing correctly, as // there is no time-out checks here in the interest of execution speed. - while self.transfer.get_transfer_complete_flag() == false {} + while !self.transfer.get_transfer_complete_flag() {} } // Start the next transfer. diff --git a/src/main.rs b/src/main.rs index ece4340..a90516c 100644 --- a/src/main.rs +++ b/src/main.rs @@ -140,6 +140,7 @@ macro_rules! route_request { match $request.attribute { $( $read_attribute => { + #[allow(clippy::redundant_closure_call)] let value = match $getter() { Ok(data) => data, Err(_) => return server::Response::error($request.attribute, @@ -168,6 +169,7 @@ macro_rules! route_request { "Failed to decode value"), }; + #[allow(clippy::redundant_closure_call)] match $setter(new_value) { Ok(_) => server::Response::success($request.attribute, &$request.value), Err(_) => server::Response::error($request.attribute, @@ -678,7 +680,7 @@ const APP: () = { dp.ETHERNET_MTL, dp.ETHERNET_DMA, &mut DES_RING, - mac_addr.clone(), + mac_addr, ccdr.peripheral.ETH1MAC, &ccdr.clocks, ) @@ -729,8 +731,8 @@ const APP: () = { sampling_timer.start(); init::LateResources { - afe0: afe0, - afe1: afe1, + afe0, + afe1, adcs, dacs, @@ -928,10 +930,12 @@ const APP: () = { } }), "stabilizer/afe0/gain": afe::Gain, (|gain| { - Ok::<(), ()>(c.resources.afe0.set_gain(gain)) + c.resources.afe0.set_gain(gain); + Ok::<(), ()>(()) }), "stabilizer/afe1/gain": afe::Gain, (|gain| { - Ok::<(), ()>(c.resources.afe1.set_gain(gain)) + c.resources.afe1.set_gain(gain); + Ok::<(), ()>(()) }) ] ) @@ -943,7 +947,7 @@ const APP: () = { &mut sockets, net::time::Instant::from_millis(time as i64), ) { - Ok(changed) => changed == false, + Ok(changed) => !changed, Err(net::Error::Unrecognized) => true, Err(e) => { info!("iface poll error: {:?}", e); diff --git a/src/pounder/mod.rs b/src/pounder/mod.rs index 6940e0e..8054243 100644 --- a/src/pounder/mod.rs +++ b/src/pounder/mod.rs @@ -17,7 +17,7 @@ const ATT_RST_N_PIN: u8 = 8 + 5; const ATT_LE3_PIN: u8 = 8 + 3; const ATT_LE2_PIN: u8 = 8 + 2; const ATT_LE1_PIN: u8 = 8 + 1; -const ATT_LE0_PIN: u8 = 8 + 0; +const ATT_LE0_PIN: u8 = 8; #[derive(Debug, Copy, Clone)] pub enum Error { diff --git a/src/server.rs b/src/server.rs index 3184426..2803805 100644 --- a/src/server.rs +++ b/src/server.rs @@ -89,7 +89,7 @@ impl Response { /// Args: /// * `attrbute` - The attribute of the success. /// * `value` - The value of the attribute. - pub fn success<'a, 'b>(attribute: &'a str, value: &'b str) -> Self { + pub fn success(attribute: &str, value: &str) -> Self { let mut res = Self { code: 200, attribute: String::from(attribute), @@ -106,7 +106,7 @@ impl Response { /// Args: /// * `attrbute` - The attribute of the success. /// * `message` - The message denoting the error. - pub fn error<'a, 'b>(attribute: &'a str, message: &'b str) -> Self { + pub fn error(attribute: &str, message: &str) -> Self { let mut res = Self { code: 400, attribute: String::from(attribute), @@ -123,7 +123,7 @@ impl Response { /// Args: /// * `attrbute` - The attribute of the success. /// * `message` - The message denoting the status. - pub fn custom<'a>(code: i32, message: &'a str) -> Self { + pub fn custom(code: i32, message: &str) -> Self { let mut res = Self { code, attribute: String::from(""),