From dac6f73d5e3e505c4e5b232fecffd37dc7e86267 Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Mon, 19 Oct 2020 17:12:02 +0200 Subject: [PATCH 01/12] WIP updates --- Cargo.lock | 44 ++++++------ Cargo.toml | 6 +- ad9959/src/lib.rs | 44 ++++++++++++ src/main.rs | 176 +++++++++++++++++++++++---------------------- src/pounder/mod.rs | 12 ++-- 5 files changed, 164 insertions(+), 118 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index 082a02c..3d3e736 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -310,9 +310,9 @@ dependencies = [ [[package]] name = "paste" -version = "0.1.17" +version = "0.1.18" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "026c63fe245362be0322bfec5a9656d458d13f9cfb1785d1b38458b9968e8080" +checksum = "45ca20c77d80be666aef2b45486da86238fabe33e38306bd3118fe4af33fa880" dependencies = [ "paste-impl", "proc-macro-hack", @@ -320,9 +320,9 @@ dependencies = [ [[package]] name = "paste-impl" -version = "0.1.17" +version = "0.1.18" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "7b9281a268ec213237dcd2aa3c3d0f46681b04ced37c1616fd36567a9e6954b0" +checksum = "d95a7db200b97ef370c8e6de0088252f7e0dfff7d047a28528e47456c0fc98b6" dependencies = [ "proc-macro-hack", ] @@ -462,7 +462,7 @@ dependencies = [ "serde-json-core", "smoltcp", "stm32h7-ethernet", - "stm32h7xx-hal 0.5.0 (git+https://github.com/quartiq/stm32h7xx-hal.git?branch=feature/pounder-support)", + "stm32h7xx-hal 0.7.1", ] [[package]] @@ -491,23 +491,7 @@ dependencies = [ "cortex-m", "log", "smoltcp", - "stm32h7xx-hal 0.5.0 (registry+https://github.com/rust-lang/crates.io-index)", -] - -[[package]] -name = "stm32h7xx-hal" -version = "0.5.0" -source = "git+https://github.com/quartiq/stm32h7xx-hal.git?branch=feature/pounder-support#ff00e938f2b226211c178f26c092f36462c44404" -dependencies = [ - "bare-metal", - "cast", - "cortex-m", - "cortex-m-rt", - "embedded-hal", - "nb 0.1.2", - "paste", - "stm32h7", - "void", + "stm32h7xx-hal 0.5.0", ] [[package]] @@ -527,6 +511,22 @@ dependencies = [ "void", ] +[[package]] +name = "stm32h7xx-hal" +version = "0.7.1" +dependencies = [ + "bare-metal", + "cast", + "cortex-m", + "cortex-m-rt", + "embedded-hal", + "nb 0.1.2", + "paste", + "smoltcp", + "stm32h7", + "void", +] + [[package]] name = "syn" version = "1.0.33" diff --git a/Cargo.toml b/Cargo.toml index 0595c33..519fc08 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -58,10 +58,8 @@ branch = "master" features = ["stm32h743v"] [dependencies.stm32h7xx-hal] -features = ["stm32h743v", "rt", "unproven"] - -[patch.crates-io] -stm32h7xx-hal = { git = "https://github.com/quartiq/stm32h7xx-hal.git", branch = "feature/pounder-support" } +features = ["stm32h743v", "rt", "unproven", "ethernet", "phy_lan8742a", "quadspi"] +path = "../stm32h7xx-hal" [features] semihosting = ["panic-semihosting", "cortex-m-log/semihosting"] diff --git a/ad9959/src/lib.rs b/ad9959/src/lib.rs index d12041c..a3d42bf 100644 --- a/ad9959/src/lib.rs +++ b/ad9959/src/lib.rs @@ -571,4 +571,48 @@ where Ok(tuning_word as f64 * self.system_clock_frequency() / (1u64 << 32) as f64) } + + pub fn write_profile(&mut self, channel: Channel, freq: f64, turns: f32) -> Result<(), Error> { + // The function for channel frequency is `f_out = FTW * f_s / 2^32`, where FTW is the + // frequency tuning word and f_s is the system clock rate. + let tuning_word: u32 = + ((freq as f64 / self.system_clock_frequency()) + * 1u64.wrapping_shl(32) as f64) as u32; + + let phase_offset: u16 = (turns * (1 << 14) as f32) as u16 & 0x3FFFu16; + + self.modify_channel_closure(channel, |interface| { + let mut data: [u8; 7] = [0; 7]; + data[0..2].copy_from_slice(&phase_offset.to_be_bytes()); + data[3] = Register::CFTW0 as u8; + data[4..7].copy_from_slice(&tuning_word.to_be_bytes()); + interface.write(Register::CPOW0 as u8, &data).map_err(|_| Error::Interface) + })?; + + Ok(()) + } + + fn modify_channel_closure(&mut self, channel: Channel, f: F) -> Result<(), Error> + where + F: FnOnce(&mut INTERFACE) -> Result<(), Error>, + { + // Disable all other outputs so that we can update the configuration register of only the + // specified channel. + let mut csr: [u8; 1] = [0]; + self.interface + .read(Register::CSR as u8, &mut csr) + .map_err(|_| Error::Interface)?; + + let mut new_csr = csr; + new_csr[0].set_bits(4..8, 0); + new_csr[0].set_bit(4 + channel as usize, true); + + let result = f(&mut self.interface); + + self.interface + .write(Register::CSR as u8, &new_csr) + .map_err(|_| Error::Interface)?; + + result + } } diff --git a/src/main.rs b/src/main.rs index 9e0c0ff..9be0830 100644 --- a/src/main.rs +++ b/src/main.rs @@ -36,7 +36,7 @@ use stm32h7xx_hal::prelude::*; use embedded_hal::digital::v2::{InputPin, OutputPin}; use smoltcp as net; -use stm32h7_ethernet as ethernet; +use hal::ethernet as ethernet; use heapless::{consts::*, String}; @@ -160,12 +160,12 @@ macro_rules! route_request { #[rtic::app(device = stm32h7xx_hal::stm32, peripherals = true, monotonic = rtic::cyccnt::CYCCNT)] const APP: () = { struct Resources { - adc0: hal::spi::Spi, - dac0: hal::spi::Spi, + adc0: hal::spi::Spi, + dac0: hal::spi::Spi, afe0: AFE0, - adc1: hal::spi::Spi, - dac1: hal::spi::Spi, + adc1: hal::spi::Spi, + dac1: hal::spi::Spi, afe1: AFE1, eeprom_i2c: hal::i2c::I2c, @@ -208,8 +208,19 @@ const APP: () = { let pwr = dp.PWR.constrain(); let vos = pwr.freeze(); + // Enable SRAM3 for the ethernet descriptor ring. + dp.RCC.ahb2enr.modify(|_, w| w.sram3en().set_bit()); + + // Clear reset flags. + dp.RCC.rsr.write(|w| w.rmvf().set_bit()); + + // Select the PLLs for SPI. + dp.RCC + .d2ccip1r + .modify(|_, w| w.spi123sel().pll2_p().spi45sel().pll2_q()); + let rcc = dp.RCC.constrain(); - let mut clocks = rcc + let clocks = rcc .use_hse(8.mhz()) .sysclk(400.mhz()) .hclk(200.mhz()) @@ -220,25 +231,15 @@ const APP: () = { init_log(); - // Enable SRAM3 for the ethernet descriptor ring. - clocks.rb.ahb2enr.modify(|_, w| w.sram3en().set_bit()); - - clocks.rb.rsr.write(|w| w.rmvf().set_bit()); - - clocks - .rb - .d2ccip1r - .modify(|_, w| w.spi123sel().pll2_p().spi45sel().pll2_q()); - let mut delay = hal::delay::Delay::new(cp.SYST, clocks.clocks); - let gpioa = dp.GPIOA.split(&mut clocks); - let gpiob = dp.GPIOB.split(&mut clocks); - let gpioc = dp.GPIOC.split(&mut clocks); - let gpiod = dp.GPIOD.split(&mut clocks); - let gpioe = dp.GPIOE.split(&mut clocks); - let gpiof = dp.GPIOF.split(&mut clocks); - let gpiog = dp.GPIOG.split(&mut clocks); + let gpioa = dp.GPIOA.split(clocks.peripheral.GPIOA); + let gpiob = dp.GPIOB.split(clocks.peripheral.GPIOB); + let gpioc = dp.GPIOC.split(clocks.peripheral.GPIOC); + let gpiod = dp.GPIOD.split(clocks.peripheral.GPIOD); + let gpioe = dp.GPIOE.split(clocks.peripheral.GPIOE); + let gpiof = dp.GPIOF.split(clocks.peripheral.GPIOF); + let gpiog = dp.GPIOG.split(clocks.peripheral.GPIOG); let afe0 = { let a0_pin = gpiof.pf2.into_push_pull_output(); @@ -274,14 +275,14 @@ const APP: () = { .communication_mode(hal::spi::CommunicationMode::Receiver) .manage_cs() .transfer_size(1) - .frame_size(16) .cs_delay(220e-9); - let mut spi = dp.SPI2.spi( + let mut spi: hal::spi::Spi<_, _, u16> = dp.SPI2.spi( (spi_sck, spi_miso, hal::spi::NoMosi), config, 50.mhz(), - &clocks, + clocks.peripheral.SPI2, + &clocks.clocks, ); spi.listen(hal::spi::Event::Eot); @@ -310,14 +311,14 @@ const APP: () = { .communication_mode(hal::spi::CommunicationMode::Receiver) .manage_cs() .transfer_size(1) - .frame_size(16) .cs_delay(220e-9); - let mut spi = dp.SPI3.spi( + let mut spi: hal::spi::Spi<_, _, u16> = dp.SPI3.spi( (spi_sck, spi_miso, hal::spi::NoMosi), config, 50.mhz(), - &clocks, + clocks.peripheral.SPI3, + &clocks.clocks, ); spi.listen(hal::spi::Event::Eot); @@ -352,14 +353,14 @@ const APP: () = { .communication_mode(hal::spi::CommunicationMode::Transmitter) .manage_cs() .transfer_size(1) - .frame_size(16) .swap_mosi_miso(); dp.SPI4.spi( (spi_sck, spi_miso, hal::spi::NoMosi), config, 50.mhz(), - &clocks, + clocks.peripheral.SPI4, + &clocks.clocks, ) }; @@ -384,14 +385,14 @@ const APP: () = { .communication_mode(hal::spi::CommunicationMode::Transmitter) .manage_cs() .transfer_size(1) - .frame_size(16) .swap_mosi_miso(); dp.SPI5.spi( (spi_sck, spi_miso, hal::spi::NoMosi), config, 50.mhz(), - &clocks, + clocks.peripheral.SPI5, + &clocks.clocks, ) }; @@ -412,36 +413,39 @@ const APP: () = { let ad9959 = { let qspi_interface = { // Instantiate the QUADSPI pins and peripheral interface. - // TODO: Place these into a pins structure that is provided to the QSPI - // constructor. - let _qspi_clk = gpiob - .pb2 - .into_alternate_af9() - .set_speed(hal::gpio::Speed::VeryHigh); - let _qspi_ncs = gpioc - .pc11 - .into_alternate_af9() - .set_speed(hal::gpio::Speed::VeryHigh); - let _qspi_io0 = gpioe - .pe7 - .into_alternate_af10() - .set_speed(hal::gpio::Speed::VeryHigh); - let _qspi_io1 = gpioe - .pe8 - .into_alternate_af10() - .set_speed(hal::gpio::Speed::VeryHigh); - let _qspi_io2 = gpioe - .pe9 - .into_alternate_af10() - .set_speed(hal::gpio::Speed::VeryHigh); - let _qspi_io3 = gpioe - .pe10 - .into_alternate_af10() - .set_speed(hal::gpio::Speed::VeryHigh); + let qspi_pins = { - let qspi = - hal::qspi::Qspi::new(dp.QUADSPI, &mut clocks, 10.mhz()) - .unwrap(); + let _qspi_ncs = gpioc + .pc11 + .into_alternate_af9() + .set_speed(hal::gpio::Speed::VeryHigh); + + let clk = gpiob + .pb2 + .into_alternate_af9() + .set_speed(hal::gpio::Speed::VeryHigh); + let io0 = gpioe + .pe7 + .into_alternate_af10() + .set_speed(hal::gpio::Speed::VeryHigh); + let io1 = gpioe + .pe8 + .into_alternate_af10() + .set_speed(hal::gpio::Speed::VeryHigh); + let io2 = gpioe + .pe9 + .into_alternate_af10() + .set_speed(hal::gpio::Speed::VeryHigh); + let io3 = gpioe + .pe10 + .into_alternate_af10() + .set_speed(hal::gpio::Speed::VeryHigh); + + (clk, io0, io1, io2, io3) + }; + + let qspi = hal::qspi::Qspi::bank2(dp.QUADSPI, qspi_pins, 11.mhz(), &clocks.clocks, + clocks.peripheral.QSPI); pounder::QspiInterface::new(qspi).unwrap() }; @@ -470,7 +474,7 @@ const APP: () = { let io_expander = { let sda = gpiob.pb7.into_alternate_af4().set_open_drain(); let scl = gpiob.pb8.into_alternate_af4().set_open_drain(); - let i2c1 = dp.I2C1.i2c((scl, sda), 100.khz(), &clocks); + let i2c1 = dp.I2C1.i2c((scl, sda), 100.khz(), clocks.peripheral.I2C1, &clocks.clocks); mcp23017::MCP23017::default(i2c1).unwrap() }; @@ -491,8 +495,7 @@ const APP: () = { let config = hal::spi::Config::new(hal::spi::Mode { polarity: hal::spi::Polarity::IdleHigh, phase: hal::spi::Phase::CaptureOnSecondTransition, - }) - .frame_size(8); + }); // The maximum frequency of this SPI must be limited due to capacitance on the MISO // line causing a long RC decay. @@ -500,22 +503,25 @@ const APP: () = { (spi_sck, spi_miso, spi_mosi), config, 5.mhz(), - &clocks, + clocks.peripheral.SPI1, + &clocks.clocks, ) }; - let adc1 = { - let mut adc = dp.ADC1.adc(&mut delay, &mut clocks); - adc.calibrate(); + let (adc1, adc2) = { + let (mut adc1, mut adc2) = hal::adc::adc12(dp.ADC1, dp.ADC2, &mut delay, clocks.peripheral.ADC12, &clocks.clocks); - adc.enable() - }; + let adc1 = { + adc1.calibrate(); + adc1.enable() + }; - let adc2 = { - let mut adc = dp.ADC2.adc(&mut delay, &mut clocks); - adc.calibrate(); + let adc2 = { + adc2.calibrate(); + adc2.enable() + }; - adc.enable() + (adc1, adc2) }; let adc1_in_p = gpiof.pf11.into_analog(); @@ -540,16 +546,16 @@ const APP: () = { let mut eeprom_i2c = { let sda = gpiof.pf0.into_alternate_af4().set_open_drain(); let scl = gpiof.pf1.into_alternate_af4().set_open_drain(); - dp.I2C2.i2c((scl, sda), 100.khz(), &clocks) + dp.I2C2.i2c((scl, sda), 100.khz(), clocks.peripheral.I2C2, &clocks.clocks) }; // Configure ethernet pins. { // Reset the PHY before configuring pins. - let mut eth_phy_nrst = gpioe.pe3.into_push_pull_output(); - eth_phy_nrst.set_low().unwrap(); - delay.delay_us(200u8); - eth_phy_nrst.set_high().unwrap(); + //let mut eth_phy_nrst = gpioe.pe3.into_push_pull_output(); + //eth_phy_nrst.set_low().unwrap(); + //delay.delay_ms(200u8); + //eth_phy_nrst.set_high().unwrap(); let _rmii_ref_clk = gpioa .pa1 .into_alternate_af11() @@ -598,8 +604,8 @@ const APP: () = { let (network_interface, eth_mac) = { // Configure the ethernet controller - let (eth_dma, eth_mac) = unsafe { - ethernet::ethernet_init( + let (eth_dma, mut eth_mac) = unsafe { + ethernet::new_unchecked( dp.ETHERNET_MAC, dp.ETHERNET_MTL, dp.ETHERNET_DMA, @@ -608,6 +614,8 @@ const APP: () = { ) }; + eth_mac.block_until_link(); + unsafe { ethernet::enable_interrupt() }; let store = unsafe { &mut NET_STORE }; @@ -638,7 +646,7 @@ const APP: () = { // Utilize the cycle counter for RTIC scheduling. cp.DWT.enable_cycle_counter(); - let mut dma = hal::dma::Dma::dma(dp.DMA1, dp.DMAMUX1, &clocks); + let mut dma = hal::dma::Dma::dma(dp.DMA1, dp.DMAMUX1, clocks.peripheral.DMA1); dma.configure_m2p_stream( hal::dma::Stream::One, &SPI_START_CODE as *const _ as u32, @@ -654,7 +662,7 @@ const APP: () = { ); // Configure timer 2 to trigger conversions for the ADC - let mut timer2 = dp.TIM2.timer(500.khz(), &mut clocks); + let mut timer2 = dp.TIM2.timer(50.khz(), clocks.peripheral.TIM2, &clocks.clocks); timer2.configure_channel(hal::timer::Channel::One, 0.25); timer2.configure_channel(hal::timer::Channel::Two, 0.75); diff --git a/src/pounder/mod.rs b/src/pounder/mod.rs index 1288765..489cc67 100644 --- a/src/pounder/mod.rs +++ b/src/pounder/mod.rs @@ -235,7 +235,7 @@ pub struct PounderDevices { hal::gpio::gpiog::PG7>, >, mcp23017: mcp23017::MCP23017>, - attenuator_spi: hal::spi::Spi, + attenuator_spi: hal::spi::Spi, adc1: hal::adc::Adc, adc2: hal::adc::Adc, adc1_in_p: hal::gpio::gpiof::PF11, @@ -262,7 +262,7 @@ where DELAY, hal::gpio::gpiog::PG7>, >, - attenuator_spi: hal::spi::Spi, + attenuator_spi: hal::spi::Spi, adc1: hal::adc::Adc, adc2: hal::adc::Adc, adc1_in_p: hal::gpio::gpiof::PF11, @@ -474,12 +474,8 @@ where channel: Channel, state: ChannelState, ) -> Result<(), Error> { - self.ad9959 - .set_frequency(channel.into(), state.parameters.frequency) - .map_err(|_| Error::Dds)?; - self.ad9959 - .set_phase(channel.into(), state.parameters.phase_offset) - .map_err(|_| Error::Dds)?; + self.ad9959.write_profile(channel.into(), state.parameters.frequency, + state.parameters.phase_offset).map_err(|_| Error::Dds)?; self.ad9959 .set_amplitude(channel.into(), state.parameters.amplitude) .map_err(|_| Error::Dds)?; From 17c8e4d2e148299639a5ea4c59e6c30806b311de Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Mon, 26 Oct 2020 16:58:29 +0100 Subject: [PATCH 02/12] Updating to new HAL --- Cargo.lock | 131 +++++++++++++++++++++++++++++++++++----------------- Cargo.toml | 3 +- src/main.rs | 77 +++++++++++++----------------- 3 files changed, 121 insertions(+), 90 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index 3d3e736..fcfc491 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -10,21 +10,22 @@ dependencies = [ [[package]] name = "aligned" -version = "0.3.2" +version = "0.3.4" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "eb1ce8b3382016136ab1d31a1b5ce807144f8b7eb2d5f16b2108f0f07edceb94" +checksum = "c19796bd8d477f1a9d4ac2465b464a8b1359474f06a96bb3cda650b4fca309bf" dependencies = [ "as-slice", ] [[package]] name = "as-slice" -version = "0.1.3" +version = "0.1.4" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "37dfb65bc03b2bc85ee827004f14a6817e04160e3b1a28931986a666a9290e70" +checksum = "bb4d1c23475b74e3672afa8c2be22040b8b7783ad9b461021144ed10a46bb0e6" dependencies = [ "generic-array 0.12.3", "generic-array 0.13.2", + "generic-array 0.14.4", "stable_deref_trait", ] @@ -41,9 +42,9 @@ dependencies = [ [[package]] name = "autocfg" -version = "1.0.0" +version = "1.0.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "f8aac770f1885fd7e387acedd76065302551364496e46b3dd00860b2f8359b9d" +checksum = "cdb031dd78e28731d87d56cc8ffef4a8f36ca26c38fe2de700543e627f8a464a" [[package]] name = "bare-metal" @@ -55,10 +56,16 @@ dependencies = [ ] [[package]] -name = "bit_field" -version = "0.10.0" +name = "bare-metal" +version = "1.0.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "a165d606cf084741d4ac3a28fb6e9b1eb0bd31f6cd999098cfddb0b2ab381dc0" +checksum = "f8fe8f5a8a398345e52358e18ff07cc17a568fbca5c6f73873d3a62056309603" + +[[package]] +name = "bit_field" +version = "0.10.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "dcb6dd1c2376d2e096796e234a70e17e94cc2d5d54ff8ce42b28cef1d0d359a4" [[package]] name = "bitfield" @@ -106,7 +113,7 @@ source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "2be99930c99669a74d986f7fd2162085498b322e6daae8ef63a97cc9ac1dc73c" dependencies = [ "aligned", - "bare-metal", + "bare-metal 0.2.5", "bitfield", "volatile-register", ] @@ -184,7 +191,7 @@ version = "0.2.4" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "fa998ce59ec9765d15216393af37a58961ddcefb14c753b4816ba2191d865fcb" dependencies = [ - "nb 0.1.2", + "nb 0.1.3", "void", ] @@ -226,6 +233,16 @@ dependencies = [ "typenum", ] +[[package]] +name = "generic-array" +version = "0.14.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "501466ecc8a30d1d3b7fc9229b122b2ce8ed6e9d9223f1138d4babb253e51817" +dependencies = [ + "typenum", + "version_check", +] + [[package]] name = "hash32" version = "0.1.1" @@ -236,10 +253,16 @@ dependencies = [ ] [[package]] -name = "heapless" -version = "0.5.5" +name = "hashbrown" +version = "0.9.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "73a8a2391a3bc70b31f60e7a90daa5755a360559c0b6b9c5cfc0fee482362dc0" +checksum = "d7afe4a420e3fe79967a00898cc1f4db7c8a49a9333a29f8a4bd76a253d5cd04" + +[[package]] +name = "heapless" +version = "0.5.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "74911a68a1658cfcfb61bc0ccfbd536e3b6e906f8c2f7883ee50157e3e2184f1" dependencies = [ "as-slice", "generic-array 0.13.2", @@ -250,11 +273,12 @@ dependencies = [ [[package]] name = "indexmap" -version = "1.4.0" +version = "1.6.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "c398b2b113b55809ceb9ee3e753fcbac793f1956663f3c36549c1346015c2afe" +checksum = "55e2e4c765aa53a0424761bf9f41aa7a6ac1efa87238f59560640e27fca028f2" dependencies = [ "autocfg", + "hashbrown", ] [[package]] @@ -282,9 +306,12 @@ dependencies = [ [[package]] name = "nb" -version = "0.1.2" +version = "0.1.3" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "b1411551beb3c11dedfb0a90a0fa256b47d28b9ec2cdff34c25a2fa59e45dbdc" +checksum = "801d31da0513b6ec5214e9bf433a77966320625a37860f910be265be6e18d06f" +dependencies = [ + "nb 1.0.0", +] [[package]] name = "nb" @@ -300,9 +327,9 @@ checksum = "de96540e0ebde571dc55c73d60ef407c653844e6f9a1e2fdbd40c07b9252d812" [[package]] name = "panic-semihosting" -version = "0.5.3" +version = "0.5.4" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "c03864ac862876c16a308f5286f4aa217f1a69ac45df87ad3cd2847f818a642c" +checksum = "aed16eb761d0ee9161dd1319cb38c8007813b20f9720a5a682b283e7b8cdfe58" dependencies = [ "cortex-m", "cortex-m-semihosting", @@ -318,6 +345,12 @@ dependencies = [ "proc-macro-hack", ] +[[package]] +name = "paste" +version = "1.0.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ba7ae1a2180ed02ddfdb5ab70c70d596a26dd642e097bb6fe78b1bde8588ed97" + [[package]] name = "paste-impl" version = "0.1.18" @@ -329,15 +362,15 @@ dependencies = [ [[package]] name = "proc-macro-hack" -version = "0.5.16" +version = "0.5.18" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "7e0456befd48169b9f13ef0f0ad46d492cf9d2dbb918bcf38e01eed4ce3ec5e4" +checksum = "99c605b9a0adc77b7211c6b1f722dcb613d68d66859a44f3d485a6da332b0598" [[package]] name = "proc-macro2" -version = "1.0.18" +version = "1.0.24" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "beae6331a816b1f65d04c45b078fd8e6c93e8071771f41b8163255bbd8d7c8fa" +checksum = "1e0704ee1a7e00d7bb417d0770ea303c1bccbabf0ef1667dae92b5967f5f8a71" dependencies = [ "unicode-xid", ] @@ -400,9 +433,9 @@ checksum = "388a1df253eca08550bef6c72392cfe7c30914bf41df5269b68cbd6ff8f570a3" [[package]] name = "serde" -version = "1.0.115" +version = "1.0.117" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "e54c9a88f2da7238af84b5101443f0c0d0a3bbdc455e34a5c9497b1903ed55d5" +checksum = "b88fa983de7720629c9387e9f517353ed404164b1e482c970a90c1a4aaf7dc1a" dependencies = [ "serde_derive", ] @@ -419,9 +452,9 @@ dependencies = [ [[package]] name = "serde_derive" -version = "1.0.115" +version = "1.0.117" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "609feed1d0a73cc36a0182a840a9b37b4a82f0b1150369f0536a9e3f2a31dc48" +checksum = "cbd1ae72adb44aab48f325a02444a5fc079349a8d804c1fc922aed3f7454c74e" dependencies = [ "proc-macro2", "quote", @@ -467,9 +500,9 @@ dependencies = [ [[package]] name = "stable_deref_trait" -version = "1.1.1" +version = "1.2.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "dba1a27d3efae4351c8051072d619e3ade2820635c3958d826bfea39d59b54c8" +checksum = "a8f112729512f8e442d81f95a8a7ddf2b7c6b8a1a6f509a95864142b30cab2d3" [[package]] name = "stm32h7" @@ -477,7 +510,18 @@ version = "0.11.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "e9beb5e2a223c82f263c3051bba4614aebc6e98bd40217df3cd8817c83ac7bd8" dependencies = [ - "bare-metal", + "bare-metal 0.2.5", + "cortex-m", + "vcell", +] + +[[package]] +name = "stm32h7" +version = "0.12.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7571f17d1ed7d67957d0004de6c52bd1ef5e736ed5ddc2bcecf001512269f77c" +dependencies = [ + "bare-metal 0.2.5", "cortex-m", "cortex-m-rt", "vcell", @@ -500,38 +544,39 @@ version = "0.5.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "987c66628f30012ed9a41cc738421c5caece03292c0cc8fd1e99956f122735bd" dependencies = [ - "bare-metal", + "bare-metal 0.2.5", "cast", "cortex-m", "cortex-m-rt", "embedded-hal", - "nb 0.1.2", - "paste", - "stm32h7", + "nb 0.1.3", + "paste 0.1.18", + "stm32h7 0.11.0", "void", ] [[package]] name = "stm32h7xx-hal" version = "0.7.1" +source = "git+https://github.com/stm32-rs/stm32h7xx-hal#f28cf3e66c7a7fe2bdd1518f06acbf680e9b9a11" dependencies = [ - "bare-metal", + "bare-metal 1.0.0", "cast", "cortex-m", "cortex-m-rt", "embedded-hal", - "nb 0.1.2", - "paste", + "nb 1.0.0", + "paste 1.0.2", "smoltcp", - "stm32h7", + "stm32h7 0.12.1", "void", ] [[package]] name = "syn" -version = "1.0.33" +version = "1.0.48" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "e8d5d96e8cbb005d6959f119f773bfaebb5684296108fb32600c00cde305b2cd" +checksum = "cc371affeffc477f42a221a1e4297aedcea33d47d19b61455588bd9d8f6b19ac" dependencies = [ "proc-macro2", "quote", @@ -546,9 +591,9 @@ checksum = "373c8a200f9e67a0c95e62a4f52fbf80c23b4381c05a17845531982fa99e6b33" [[package]] name = "unicode-xid" -version = "0.2.0" +version = "0.2.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "826e7639553986605ec5979c7dd957c7895e93eabed50ab2ffa7f6128a75097c" +checksum = "f7fe0bb3479651439c9112f72b6c505038574c9fbb575ed1bf3b797fa39dd564" [[package]] name = "vcell" diff --git a/Cargo.toml b/Cargo.toml index 519fc08..fe4cda3 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -59,7 +59,8 @@ features = ["stm32h743v"] [dependencies.stm32h7xx-hal] features = ["stm32h743v", "rt", "unproven", "ethernet", "phy_lan8742a", "quadspi"] -path = "../stm32h7xx-hal" +git = "https://github.com/stm32-rs/stm32h7xx-hal" +# path = "../stm32h7xx-hal" [features] semihosting = ["panic-semihosting", "cortex-m-log/semihosting"] diff --git a/src/main.rs b/src/main.rs index 9be0830..3b5bfd1 100644 --- a/src/main.rs +++ b/src/main.rs @@ -36,7 +36,10 @@ use stm32h7xx_hal::prelude::*; use embedded_hal::digital::v2::{InputPin, OutputPin}; use smoltcp as net; -use hal::ethernet as ethernet; +use hal::{ + ethernet, + dma::{DmaExt, DmaChannel, DmaInternal}, +}; use heapless::{consts::*, String}; @@ -253,6 +256,8 @@ const APP: () = { afe::ProgrammableGainAmplifier::new(a0_pin, a1_pin) }; + let mut dma_channels = dp.DMA1.split(); + // Configure the SPI interfaces to the ADCs and DACs. let adc0_spi = { let spi_miso = gpiob @@ -272,11 +277,18 @@ const APP: () = { polarity: hal::spi::Polarity::IdleHigh, phase: hal::spi::Phase::CaptureOnSecondTransition, }) - .communication_mode(hal::spi::CommunicationMode::Receiver) .manage_cs() - .transfer_size(1) .cs_delay(220e-9); + dma_channels.0.set_peripheral_address(&dp.SPI2.cr1 as *const _ as u32, false); + dma_channels.0.set_memory_address(&SPI_START_CODE as *const _ as u32, false); + dma_channels.0.set_direction(hal::dma::Direction::MemoryToPeripherial); + dma_channels.0.set_transfer_length(1); + dma_channels.0.cr().modify(|_, w| w.circ().enabled()); + dma_channels.0.dmamux().modify(|_, w| + w.dmareq_id().variant(hal::stm32::dmamux1::ccr::DMAREQ_ID_A::TIM2_UP)); + dma_channels.0.start(); + let mut spi: hal::spi::Spi<_, _, u16> = dp.SPI2.spi( (spi_sck, spi_miso, hal::spi::NoMosi), config, @@ -285,7 +297,7 @@ const APP: () = { &clocks.clocks, ); - spi.listen(hal::spi::Event::Eot); + spi.listen(hal::spi::Event::Rxp); spi }; @@ -308,11 +320,18 @@ const APP: () = { polarity: hal::spi::Polarity::IdleHigh, phase: hal::spi::Phase::CaptureOnSecondTransition, }) - .communication_mode(hal::spi::CommunicationMode::Receiver) .manage_cs() - .transfer_size(1) .cs_delay(220e-9); + dma_channels.1.set_peripheral_address(&dp.SPI3.cr1 as *const _ as u32, false); + dma_channels.1.set_memory_address(&SPI_START_CODE as *const _ as u32, false); + dma_channels.1.set_direction(hal::dma::Direction::MemoryToPeripherial); + dma_channels.1.dmamux().modify(|_, w| + w.dmareq_id().variant(hal::stm32::dmamux1::ccr::DMAREQ_ID_A::TIM2_UP)); + dma_channels.1.set_transfer_length(1); + dma_channels.1.cr().modify(|_, w| w.circ().enabled()); + dma_channels.1.start(); + let mut spi: hal::spi::Spi<_, _, u16> = dp.SPI3.spi( (spi_sck, spi_miso, hal::spi::NoMosi), config, @@ -321,7 +340,7 @@ const APP: () = { &clocks.clocks, ); - spi.listen(hal::spi::Event::Eot); + spi.listen(hal::spi::Event::Rxp); spi }; @@ -350,9 +369,7 @@ const APP: () = { polarity: hal::spi::Polarity::IdleHigh, phase: hal::spi::Phase::CaptureOnSecondTransition, }) - .communication_mode(hal::spi::CommunicationMode::Transmitter) .manage_cs() - .transfer_size(1) .swap_mosi_miso(); dp.SPI4.spi( @@ -382,9 +399,7 @@ const APP: () = { polarity: hal::spi::Polarity::IdleHigh, phase: hal::spi::Phase::CaptureOnSecondTransition, }) - .communication_mode(hal::spi::CommunicationMode::Transmitter) .manage_cs() - .transfer_size(1) .swap_mosi_miso(); dp.SPI5.spi( @@ -646,28 +661,12 @@ const APP: () = { // Utilize the cycle counter for RTIC scheduling. cp.DWT.enable_cycle_counter(); - let mut dma = hal::dma::Dma::dma(dp.DMA1, dp.DMAMUX1, clocks.peripheral.DMA1); - dma.configure_m2p_stream( - hal::dma::Stream::One, - &SPI_START_CODE as *const _ as u32, - &adc0_spi.spi.cr1 as *const _ as u32, - hal::dma::DMAREQ_ID::TIM2_CH1, - ); - - dma.configure_m2p_stream( - hal::dma::Stream::Two, - &SPI_START_CODE as *const _ as u32, - &adc1_spi.spi.cr1 as *const _ as u32, - hal::dma::DMAREQ_ID::TIM2_CH2, - ); - // Configure timer 2 to trigger conversions for the ADC - let mut timer2 = dp.TIM2.timer(50.khz(), clocks.peripheral.TIM2, &clocks.clocks); - timer2.configure_channel(hal::timer::Channel::One, 0.25); - timer2.configure_channel(hal::timer::Channel::Two, 0.75); - - timer2.listen(hal::timer::Event::ChannelOneDma); - timer2.listen(hal::timer::Event::ChannelTwoDma); + let timer2 = dp.TIM2.timer(500.khz(), clocks.peripheral.TIM2, &clocks.clocks); + { + let t2_regs = unsafe { &*hal::stm32::TIM2::ptr() }; + t2_regs.dier.modify(|_, w| w.ude().set_bit()); + } init::LateResources { afe0: afe0, @@ -690,8 +689,6 @@ const APP: () = { #[task(binds = SPI3, resources = [adc1, dac1, iir_state, iir_ch], priority = 2)] fn spi3(c: spi3::Context) { - c.resources.adc1.spi.ifcr.write(|w| w.eotc().set_bit()); - let output: u16 = { let a: u16 = c.resources.adc1.read().unwrap(); let x0 = f32::from(a as i16); @@ -700,18 +697,11 @@ const APP: () = { y0 as i16 as u16 ^ 0x8000 }; - c.resources - .dac1 - .spi - .ifcr - .write(|w| w.eotc().set_bit().txtfc().set_bit()); c.resources.dac1.send(output).unwrap(); } #[task(binds = SPI2, resources = [adc0, dac0, iir_state, iir_ch], priority = 2)] fn spi2(c: spi2::Context) { - c.resources.adc0.spi.ifcr.write(|w| w.eotc().set_bit()); - let output: u16 = { let a: u16 = c.resources.adc0.read().unwrap(); let x0 = f32::from(a as i16); @@ -720,11 +710,6 @@ const APP: () = { y0 as i16 as u16 ^ 0x8000 }; - c.resources - .dac0 - .spi - .ifcr - .write(|w| w.eotc().set_bit().txtfc().set_bit()); c.resources.dac0.send(output).unwrap(); } From c058d4bcdee2f42d5fc9d21119edf4792a1c820e Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Wed, 28 Oct 2020 15:41:27 +0100 Subject: [PATCH 03/12] Adding updates for 0.8.0 of the HAL --- Cargo.lock | 14 ++--- Cargo.toml | 6 +- ad9959/src/lib.rs | 23 +++++-- src/main.rs | 145 ++++++++++++++++++++++++++++++++------------- src/pounder/mod.rs | 9 ++- 5 files changed, 139 insertions(+), 58 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index fcfc491..998e749 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -108,9 +108,9 @@ checksum = "4785bdd1c96b2a846b2bd7cc02e86b6b3dbf14e7e53446c4f54c92a361040822" [[package]] name = "cortex-m" -version = "0.6.3" +version = "0.6.4" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "2be99930c99669a74d986f7fd2162085498b322e6daae8ef63a97cc9ac1dc73c" +checksum = "88cdafeafba636c00c467ded7f1587210725a1adfab0c24028a7844b87738263" dependencies = [ "aligned", "bare-metal 0.2.5", @@ -362,9 +362,9 @@ dependencies = [ [[package]] name = "proc-macro-hack" -version = "0.5.18" +version = "0.5.19" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "99c605b9a0adc77b7211c6b1f722dcb613d68d66859a44f3d485a6da332b0598" +checksum = "dbf0c48bc1d91375ae5c3cd81e3722dff1abcf81a30960240640d223f59fe0e5" [[package]] name = "proc-macro2" @@ -495,7 +495,7 @@ dependencies = [ "serde-json-core", "smoltcp", "stm32h7-ethernet", - "stm32h7xx-hal 0.7.1", + "stm32h7xx-hal 0.8.0", ] [[package]] @@ -557,8 +557,8 @@ dependencies = [ [[package]] name = "stm32h7xx-hal" -version = "0.7.1" -source = "git+https://github.com/stm32-rs/stm32h7xx-hal#f28cf3e66c7a7fe2bdd1518f06acbf680e9b9a11" +version = "0.8.0" +source = "git+https://github.com/quartiq/stm32h7xx-hal?branch=rs/issue-158/managed-spi#cc36bbbaa1bf21e53732cfc0f3dd7175c3ed6d44" dependencies = [ "bare-metal 1.0.0", "cast", diff --git a/Cargo.toml b/Cargo.toml index fe4cda3..0f2df5c 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -58,9 +58,9 @@ branch = "master" features = ["stm32h743v"] [dependencies.stm32h7xx-hal] -features = ["stm32h743v", "rt", "unproven", "ethernet", "phy_lan8742a", "quadspi"] -git = "https://github.com/stm32-rs/stm32h7xx-hal" -# path = "../stm32h7xx-hal" +features = ["stm32h743v", "rt", "unproven", "ethernet", "quadspi"] +git = "https://github.com/quartiq/stm32h7xx-hal" +branch = "rs/issue-158/managed-spi" [features] semihosting = ["panic-semihosting", "cortex-m-log/semihosting"] diff --git a/ad9959/src/lib.rs b/ad9959/src/lib.rs index a3d42bf..6fdcefd 100644 --- a/ad9959/src/lib.rs +++ b/ad9959/src/lib.rs @@ -572,12 +572,17 @@ where / (1u64 << 32) as f64) } - pub fn write_profile(&mut self, channel: Channel, freq: f64, turns: f32) -> Result<(), Error> { + pub fn write_profile( + &mut self, + channel: Channel, + freq: f64, + turns: f32, + ) -> Result<(), Error> { // The function for channel frequency is `f_out = FTW * f_s / 2^32`, where FTW is the // frequency tuning word and f_s is the system clock rate. - let tuning_word: u32 = - ((freq as f64 / self.system_clock_frequency()) - * 1u64.wrapping_shl(32) as f64) as u32; + let tuning_word: u32 = ((freq as f64 / self.system_clock_frequency()) + * 1u64.wrapping_shl(32) as f64) + as u32; let phase_offset: u16 = (turns * (1 << 14) as f32) as u16 & 0x3FFFu16; @@ -586,13 +591,19 @@ where data[0..2].copy_from_slice(&phase_offset.to_be_bytes()); data[3] = Register::CFTW0 as u8; data[4..7].copy_from_slice(&tuning_word.to_be_bytes()); - interface.write(Register::CPOW0 as u8, &data).map_err(|_| Error::Interface) + interface + .write(Register::CPOW0 as u8, &data) + .map_err(|_| Error::Interface) })?; Ok(()) } - fn modify_channel_closure(&mut self, channel: Channel, f: F) -> Result<(), Error> + fn modify_channel_closure( + &mut self, + channel: Channel, + f: F, + ) -> Result<(), Error> where F: FnOnce(&mut INTERFACE) -> Result<(), Error>, { diff --git a/src/main.rs b/src/main.rs index 3b5bfd1..61dcb7e 100644 --- a/src/main.rs +++ b/src/main.rs @@ -1,4 +1,3 @@ -#![deny(warnings)] #![allow(clippy::missing_safety_doc)] #![no_std] #![no_main] @@ -35,11 +34,12 @@ use stm32h7xx_hal::prelude::*; use embedded_hal::digital::v2::{InputPin, OutputPin}; -use smoltcp as net; use hal::{ + dma::{DmaChannel, DmaExt, DmaInternal}, ethernet, - dma::{DmaExt, DmaChannel, DmaInternal}, + rcc::rec::ResetEnable, }; +use smoltcp as net; use heapless::{consts::*, String}; @@ -92,7 +92,7 @@ static mut NET_STORE: NetStorage = NetStorage { const SCALE: f32 = ((1 << 15) - 1) as f32; -const SPI_START_CODE: u32 = 0x201; +const SPI_START: u32 = 0x00; // static ETHERNET_PENDING: AtomicBool = AtomicBool::new(true); @@ -176,22 +176,13 @@ const APP: () = { timer: hal::timer::Timer, // Note: It appears that rustfmt generates a format that GDB cannot recognize, which - // results in GDB breakpoints being set improperly. To debug, redefine the following - // definition to: - // - // ```rust - // net_interface: net::iface::EthernetInterface< - // 'static, - // 'static, - // 'static, - // ethernet::EthernetDMA<'static>>, - // ``` + // results in GDB breakpoints being set improperly. + #[rustfmt::skip] net_interface: net::iface::EthernetInterface< 'static, 'static, 'static, - ethernet::EthernetDMA<'static>, - >, + ethernet::EthernetDMA<'static>>, eth_mac: ethernet::EthernetMAC, mac_addr: net::wire::EthernetAddress, @@ -256,6 +247,7 @@ const APP: () = { afe::ProgrammableGainAmplifier::new(a0_pin, a1_pin) }; + clocks.peripheral.DMA1.reset().enable(); let mut dma_channels = dp.DMA1.split(); // Configure the SPI interfaces to the ADCs and DACs. @@ -278,16 +270,34 @@ const APP: () = { phase: hal::spi::Phase::CaptureOnSecondTransition, }) .manage_cs() + .suspend_when_inactive() .cs_delay(220e-9); - dma_channels.0.set_peripheral_address(&dp.SPI2.cr1 as *const _ as u32, false); - dma_channels.0.set_memory_address(&SPI_START_CODE as *const _ as u32, false); - dma_channels.0.set_direction(hal::dma::Direction::MemoryToPeripherial); + dma_channels.0.set_peripheral_address( + &dp.SPI2.txdr as *const _ as u32, + false, + ); + dma_channels + .0 + .set_memory_address(&SPI_START as *const _ as u32, false); + dma_channels + .0 + .set_direction(hal::dma::Direction::MemoryToPeripherial); dma_channels.0.set_transfer_length(1); - dma_channels.0.cr().modify(|_, w| w.circ().enabled()); - dma_channels.0.dmamux().modify(|_, w| - w.dmareq_id().variant(hal::stm32::dmamux1::ccr::DMAREQ_ID_A::TIM2_UP)); - dma_channels.0.start(); + dma_channels.0.cr().modify(|_, w| { + w.circ() + .enabled() + .psize() + .bits16() + .msize() + .bits16() + .pfctrl() + .dma() + }); + dma_channels.0.dmamux().modify(|_, w| { + w.dmareq_id() + .variant(hal::stm32::dmamux1::ccr::DMAREQ_ID_A::TIM2_UP) + }); let mut spi: hal::spi::Spi<_, _, u16> = dp.SPI2.spi( (spi_sck, spi_miso, hal::spi::NoMosi), @@ -297,6 +307,10 @@ const APP: () = { &clocks.clocks, ); + // Kick-start the SPI transaction - we will add data to the TXFIFO to read from the ADC. + let spi_regs = unsafe { &*hal::stm32::SPI2::ptr() }; + spi_regs.cr1.modify(|_, w| w.cstart().started()); + spi.listen(hal::spi::Event::Rxp); spi @@ -321,16 +335,34 @@ const APP: () = { phase: hal::spi::Phase::CaptureOnSecondTransition, }) .manage_cs() + .suspend_when_inactive() .cs_delay(220e-9); - dma_channels.1.set_peripheral_address(&dp.SPI3.cr1 as *const _ as u32, false); - dma_channels.1.set_memory_address(&SPI_START_CODE as *const _ as u32, false); - dma_channels.1.set_direction(hal::dma::Direction::MemoryToPeripherial); - dma_channels.1.dmamux().modify(|_, w| - w.dmareq_id().variant(hal::stm32::dmamux1::ccr::DMAREQ_ID_A::TIM2_UP)); + dma_channels.1.set_peripheral_address( + &dp.SPI3.txdr as *const _ as u32, + false, + ); + dma_channels + .1 + .set_memory_address(&SPI_START as *const _ as u32, false); + dma_channels + .1 + .set_direction(hal::dma::Direction::MemoryToPeripherial); + dma_channels.1.dmamux().modify(|_, w| { + w.dmareq_id() + .variant(hal::stm32::dmamux1::ccr::DMAREQ_ID_A::TIM2_UP) + }); dma_channels.1.set_transfer_length(1); - dma_channels.1.cr().modify(|_, w| w.circ().enabled()); - dma_channels.1.start(); + dma_channels.1.cr().modify(|_, w| { + w.circ() + .enabled() + .psize() + .bits16() + .msize() + .bits16() + .pfctrl() + .dma() + }); let mut spi: hal::spi::Spi<_, _, u16> = dp.SPI3.spi( (spi_sck, spi_miso, hal::spi::NoMosi), @@ -340,6 +372,9 @@ const APP: () = { &clocks.clocks, ); + let spi_regs = unsafe { &*hal::stm32::SPI3::ptr() }; + spi_regs.cr1.modify(|_, w| w.cstart().started()); + spi.listen(hal::spi::Event::Rxp); spi @@ -370,6 +405,8 @@ const APP: () = { phase: hal::spi::Phase::CaptureOnSecondTransition, }) .manage_cs() + .suspend_when_inactive() + .communication_mode(hal::spi::CommunicationMode::Transmitter) .swap_mosi_miso(); dp.SPI4.spi( @@ -400,6 +437,8 @@ const APP: () = { phase: hal::spi::Phase::CaptureOnSecondTransition, }) .manage_cs() + .suspend_when_inactive() + .communication_mode(hal::spi::CommunicationMode::Transmitter) .swap_mosi_miso(); dp.SPI5.spi( @@ -429,7 +468,6 @@ const APP: () = { let qspi_interface = { // Instantiate the QUADSPI pins and peripheral interface. let qspi_pins = { - let _qspi_ncs = gpioc .pc11 .into_alternate_af9() @@ -459,8 +497,13 @@ const APP: () = { (clk, io0, io1, io2, io3) }; - let qspi = hal::qspi::Qspi::bank2(dp.QUADSPI, qspi_pins, 11.mhz(), &clocks.clocks, - clocks.peripheral.QSPI); + let qspi = hal::qspi::Qspi::bank2( + dp.QUADSPI, + qspi_pins, + 11.mhz(), + &clocks.clocks, + clocks.peripheral.QSPI, + ); pounder::QspiInterface::new(qspi).unwrap() }; @@ -489,7 +532,12 @@ const APP: () = { let io_expander = { let sda = gpiob.pb7.into_alternate_af4().set_open_drain(); let scl = gpiob.pb8.into_alternate_af4().set_open_drain(); - let i2c1 = dp.I2C1.i2c((scl, sda), 100.khz(), clocks.peripheral.I2C1, &clocks.clocks); + let i2c1 = dp.I2C1.i2c( + (scl, sda), + 100.khz(), + clocks.peripheral.I2C1, + &clocks.clocks, + ); mcp23017::MCP23017::default(i2c1).unwrap() }; @@ -524,7 +572,13 @@ const APP: () = { }; let (adc1, adc2) = { - let (mut adc1, mut adc2) = hal::adc::adc12(dp.ADC1, dp.ADC2, &mut delay, clocks.peripheral.ADC12, &clocks.clocks); + let (mut adc1, mut adc2) = hal::adc::adc12( + dp.ADC1, + dp.ADC2, + &mut delay, + clocks.peripheral.ADC12, + &clocks.clocks, + ); let adc1 = { adc1.calibrate(); @@ -561,7 +615,12 @@ const APP: () = { let mut eeprom_i2c = { let sda = gpiof.pf0.into_alternate_af4().set_open_drain(); let scl = gpiof.pf1.into_alternate_af4().set_open_drain(); - dp.I2C2.i2c((scl, sda), 100.khz(), clocks.peripheral.I2C2, &clocks.clocks) + dp.I2C2.i2c( + (scl, sda), + 100.khz(), + clocks.peripheral.I2C2, + &clocks.clocks, + ) }; // Configure ethernet pins. @@ -619,18 +678,18 @@ const APP: () = { let (network_interface, eth_mac) = { // Configure the ethernet controller - let (eth_dma, mut eth_mac) = unsafe { + let (eth_dma, eth_mac) = unsafe { ethernet::new_unchecked( dp.ETHERNET_MAC, dp.ETHERNET_MTL, dp.ETHERNET_DMA, &mut DES_RING, mac_addr.clone(), + clocks.peripheral.ETH1MAC, + &clocks.clocks, ) }; - eth_mac.block_until_link(); - unsafe { ethernet::enable_interrupt() }; let store = unsafe { &mut NET_STORE }; @@ -662,12 +721,18 @@ const APP: () = { cp.DWT.enable_cycle_counter(); // Configure timer 2 to trigger conversions for the ADC - let timer2 = dp.TIM2.timer(500.khz(), clocks.peripheral.TIM2, &clocks.clocks); + let timer2 = + dp.TIM2 + .timer(500.khz(), clocks.peripheral.TIM2, &clocks.clocks); { let t2_regs = unsafe { &*hal::stm32::TIM2::ptr() }; t2_regs.dier.modify(|_, w| w.ude().set_bit()); } + // Start the SPI transfers. + dma_channels.0.start(); + dma_channels.1.start(); + init::LateResources { afe0: afe0, adc0: adc0_spi, diff --git a/src/pounder/mod.rs b/src/pounder/mod.rs index 489cc67..032b209 100644 --- a/src/pounder/mod.rs +++ b/src/pounder/mod.rs @@ -474,8 +474,13 @@ where channel: Channel, state: ChannelState, ) -> Result<(), Error> { - self.ad9959.write_profile(channel.into(), state.parameters.frequency, - state.parameters.phase_offset).map_err(|_| Error::Dds)?; + self.ad9959 + .write_profile( + channel.into(), + state.parameters.frequency, + state.parameters.phase_offset, + ) + .map_err(|_| Error::Dds)?; self.ad9959 .set_amplitude(channel.into(), state.parameters.amplitude) .map_err(|_| Error::Dds)?; From b4eeeb20423ff46c8d6b622ecbb7a0886b50d227 Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Wed, 28 Oct 2020 15:44:52 +0100 Subject: [PATCH 04/12] Reverting unneeded changes --- ad9959/src/lib.rs | 55 ---------------------------------------------- src/main.rs | 8 +++---- src/pounder/mod.rs | 13 +++++------ 3 files changed, 10 insertions(+), 66 deletions(-) diff --git a/ad9959/src/lib.rs b/ad9959/src/lib.rs index 6fdcefd..d12041c 100644 --- a/ad9959/src/lib.rs +++ b/ad9959/src/lib.rs @@ -571,59 +571,4 @@ where Ok(tuning_word as f64 * self.system_clock_frequency() / (1u64 << 32) as f64) } - - pub fn write_profile( - &mut self, - channel: Channel, - freq: f64, - turns: f32, - ) -> Result<(), Error> { - // The function for channel frequency is `f_out = FTW * f_s / 2^32`, where FTW is the - // frequency tuning word and f_s is the system clock rate. - let tuning_word: u32 = ((freq as f64 / self.system_clock_frequency()) - * 1u64.wrapping_shl(32) as f64) - as u32; - - let phase_offset: u16 = (turns * (1 << 14) as f32) as u16 & 0x3FFFu16; - - self.modify_channel_closure(channel, |interface| { - let mut data: [u8; 7] = [0; 7]; - data[0..2].copy_from_slice(&phase_offset.to_be_bytes()); - data[3] = Register::CFTW0 as u8; - data[4..7].copy_from_slice(&tuning_word.to_be_bytes()); - interface - .write(Register::CPOW0 as u8, &data) - .map_err(|_| Error::Interface) - })?; - - Ok(()) - } - - fn modify_channel_closure( - &mut self, - channel: Channel, - f: F, - ) -> Result<(), Error> - where - F: FnOnce(&mut INTERFACE) -> Result<(), Error>, - { - // Disable all other outputs so that we can update the configuration register of only the - // specified channel. - let mut csr: [u8; 1] = [0]; - self.interface - .read(Register::CSR as u8, &mut csr) - .map_err(|_| Error::Interface)?; - - let mut new_csr = csr; - new_csr[0].set_bits(4..8, 0); - new_csr[0].set_bit(4 + channel as usize, true); - - let result = f(&mut self.interface); - - self.interface - .write(Register::CSR as u8, &new_csr) - .map_err(|_| Error::Interface)?; - - result - } } diff --git a/src/main.rs b/src/main.rs index 61dcb7e..2b0e240 100644 --- a/src/main.rs +++ b/src/main.rs @@ -626,10 +626,10 @@ const APP: () = { // Configure ethernet pins. { // Reset the PHY before configuring pins. - //let mut eth_phy_nrst = gpioe.pe3.into_push_pull_output(); - //eth_phy_nrst.set_low().unwrap(); - //delay.delay_ms(200u8); - //eth_phy_nrst.set_high().unwrap(); + let mut eth_phy_nrst = gpioe.pe3.into_push_pull_output(); + eth_phy_nrst.set_low().unwrap(); + delay.delay_us(200u8); + eth_phy_nrst.set_high().unwrap(); let _rmii_ref_clk = gpioa .pa1 .into_alternate_af11() diff --git a/src/pounder/mod.rs b/src/pounder/mod.rs index 032b209..1288765 100644 --- a/src/pounder/mod.rs +++ b/src/pounder/mod.rs @@ -235,7 +235,7 @@ pub struct PounderDevices { hal::gpio::gpiog::PG7>, >, mcp23017: mcp23017::MCP23017>, - attenuator_spi: hal::spi::Spi, + attenuator_spi: hal::spi::Spi, adc1: hal::adc::Adc, adc2: hal::adc::Adc, adc1_in_p: hal::gpio::gpiof::PF11, @@ -262,7 +262,7 @@ where DELAY, hal::gpio::gpiog::PG7>, >, - attenuator_spi: hal::spi::Spi, + attenuator_spi: hal::spi::Spi, adc1: hal::adc::Adc, adc2: hal::adc::Adc, adc1_in_p: hal::gpio::gpiof::PF11, @@ -475,11 +475,10 @@ where state: ChannelState, ) -> Result<(), Error> { self.ad9959 - .write_profile( - channel.into(), - state.parameters.frequency, - state.parameters.phase_offset, - ) + .set_frequency(channel.into(), state.parameters.frequency) + .map_err(|_| Error::Dds)?; + self.ad9959 + .set_phase(channel.into(), state.parameters.phase_offset) .map_err(|_| Error::Dds)?; self.ad9959 .set_amplitude(channel.into(), state.parameters.amplitude) From e36b853dc8d3fea5c44ae4ca126632c54b9b5cc5 Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Wed, 28 Oct 2020 15:51:08 +0100 Subject: [PATCH 05/12] Renaming clocks to ccdr --- src/main.rs | 65 ++++++++++++++++++++++++++--------------------------- 1 file changed, 32 insertions(+), 33 deletions(-) diff --git a/src/main.rs b/src/main.rs index 2b0e240..a791457 100644 --- a/src/main.rs +++ b/src/main.rs @@ -214,7 +214,7 @@ const APP: () = { .modify(|_, w| w.spi123sel().pll2_p().spi45sel().pll2_q()); let rcc = dp.RCC.constrain(); - let clocks = rcc + let ccdr = rcc .use_hse(8.mhz()) .sysclk(400.mhz()) .hclk(200.mhz()) @@ -225,15 +225,15 @@ const APP: () = { init_log(); - let mut delay = hal::delay::Delay::new(cp.SYST, clocks.clocks); + let mut delay = hal::delay::Delay::new(cp.SYST, ccdr.clocks); - let gpioa = dp.GPIOA.split(clocks.peripheral.GPIOA); - let gpiob = dp.GPIOB.split(clocks.peripheral.GPIOB); - let gpioc = dp.GPIOC.split(clocks.peripheral.GPIOC); - let gpiod = dp.GPIOD.split(clocks.peripheral.GPIOD); - let gpioe = dp.GPIOE.split(clocks.peripheral.GPIOE); - let gpiof = dp.GPIOF.split(clocks.peripheral.GPIOF); - let gpiog = dp.GPIOG.split(clocks.peripheral.GPIOG); + let gpioa = dp.GPIOA.split(ccdr.peripheral.GPIOA); + let gpiob = dp.GPIOB.split(ccdr.peripheral.GPIOB); + let gpioc = dp.GPIOC.split(ccdr.peripheral.GPIOC); + let gpiod = dp.GPIOD.split(ccdr.peripheral.GPIOD); + let gpioe = dp.GPIOE.split(ccdr.peripheral.GPIOE); + let gpiof = dp.GPIOF.split(ccdr.peripheral.GPIOF); + let gpiog = dp.GPIOG.split(ccdr.peripheral.GPIOG); let afe0 = { let a0_pin = gpiof.pf2.into_push_pull_output(); @@ -247,7 +247,7 @@ const APP: () = { afe::ProgrammableGainAmplifier::new(a0_pin, a1_pin) }; - clocks.peripheral.DMA1.reset().enable(); + ccdr.peripheral.DMA1.reset().enable(); let mut dma_channels = dp.DMA1.split(); // Configure the SPI interfaces to the ADCs and DACs. @@ -303,8 +303,8 @@ const APP: () = { (spi_sck, spi_miso, hal::spi::NoMosi), config, 50.mhz(), - clocks.peripheral.SPI2, - &clocks.clocks, + ccdr.peripheral.SPI2, + &ccdr.clocks, ); // Kick-start the SPI transaction - we will add data to the TXFIFO to read from the ADC. @@ -368,8 +368,8 @@ const APP: () = { (spi_sck, spi_miso, hal::spi::NoMosi), config, 50.mhz(), - clocks.peripheral.SPI3, - &clocks.clocks, + ccdr.peripheral.SPI3, + &ccdr.clocks, ); let spi_regs = unsafe { &*hal::stm32::SPI3::ptr() }; @@ -413,8 +413,8 @@ const APP: () = { (spi_sck, spi_miso, hal::spi::NoMosi), config, 50.mhz(), - clocks.peripheral.SPI4, - &clocks.clocks, + ccdr.peripheral.SPI4, + &ccdr.clocks, ) }; @@ -445,8 +445,8 @@ const APP: () = { (spi_sck, spi_miso, hal::spi::NoMosi), config, 50.mhz(), - clocks.peripheral.SPI5, - &clocks.clocks, + ccdr.peripheral.SPI5, + &ccdr.clocks, ) }; @@ -501,8 +501,8 @@ const APP: () = { dp.QUADSPI, qspi_pins, 11.mhz(), - &clocks.clocks, - clocks.peripheral.QSPI, + &ccdr.clocks, + ccdr.peripheral.QSPI, ); pounder::QspiInterface::new(qspi).unwrap() }; @@ -511,7 +511,7 @@ const APP: () = { let io_update = gpiog.pg7.into_push_pull_output(); let asm_delay = { - let frequency_hz = clocks.clocks.c_ck().0; + let frequency_hz = ccdr.ccdr.c_ck().0; asm_delay::AsmDelay::new(asm_delay::bitrate::Hertz( frequency_hz, )) @@ -535,8 +535,8 @@ const APP: () = { let i2c1 = dp.I2C1.i2c( (scl, sda), 100.khz(), - clocks.peripheral.I2C1, - &clocks.clocks, + ccdr.peripheral.I2C1, + &ccdr.clocks, ); mcp23017::MCP23017::default(i2c1).unwrap() }; @@ -566,8 +566,8 @@ const APP: () = { (spi_sck, spi_miso, spi_mosi), config, 5.mhz(), - clocks.peripheral.SPI1, - &clocks.clocks, + ccdr.peripheral.SPI1, + &ccdr.clocks, ) }; @@ -576,8 +576,8 @@ const APP: () = { dp.ADC1, dp.ADC2, &mut delay, - clocks.peripheral.ADC12, - &clocks.clocks, + ccdr.peripheral.ADC12, + &ccdr.clocks, ); let adc1 = { @@ -618,8 +618,8 @@ const APP: () = { dp.I2C2.i2c( (scl, sda), 100.khz(), - clocks.peripheral.I2C2, - &clocks.clocks, + ccdr.peripheral.I2C2, + &ccdr.clocks, ) }; @@ -685,8 +685,8 @@ const APP: () = { dp.ETHERNET_DMA, &mut DES_RING, mac_addr.clone(), - clocks.peripheral.ETH1MAC, - &clocks.clocks, + ccdr.peripheral.ETH1MAC, + &ccdr.clocks, ) }; @@ -722,8 +722,7 @@ const APP: () = { // Configure timer 2 to trigger conversions for the ADC let timer2 = - dp.TIM2 - .timer(500.khz(), clocks.peripheral.TIM2, &clocks.clocks); + dp.TIM2.timer(500.khz(), ccdr.peripheral.TIM2, &ccdr.clocks); { let t2_regs = unsafe { &*hal::stm32::TIM2::ptr() }; t2_regs.dier.modify(|_, w| w.ude().set_bit()); From 11ff93e6f0a080a1239de0d44bf3fd5040cab11c Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Wed, 28 Oct 2020 15:57:14 +0100 Subject: [PATCH 06/12] Fixing diff --- src/main.rs | 4 ++-- src/pounder/mod.rs | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/main.rs b/src/main.rs index a791457..c7d0eaa 100644 --- a/src/main.rs +++ b/src/main.rs @@ -500,7 +500,7 @@ const APP: () = { let qspi = hal::qspi::Qspi::bank2( dp.QUADSPI, qspi_pins, - 11.mhz(), + 10.mhz(), &ccdr.clocks, ccdr.peripheral.QSPI, ); @@ -511,7 +511,7 @@ const APP: () = { let io_update = gpiog.pg7.into_push_pull_output(); let asm_delay = { - let frequency_hz = ccdr.ccdr.c_ck().0; + let frequency_hz = ccdr.clocks.c_ck().0; asm_delay::AsmDelay::new(asm_delay::bitrate::Hertz( frequency_hz, )) diff --git a/src/pounder/mod.rs b/src/pounder/mod.rs index 1288765..6940e0e 100644 --- a/src/pounder/mod.rs +++ b/src/pounder/mod.rs @@ -235,7 +235,7 @@ pub struct PounderDevices { hal::gpio::gpiog::PG7>, >, mcp23017: mcp23017::MCP23017>, - attenuator_spi: hal::spi::Spi, + attenuator_spi: hal::spi::Spi, adc1: hal::adc::Adc, adc2: hal::adc::Adc, adc1_in_p: hal::gpio::gpiof::PF11, @@ -262,7 +262,7 @@ where DELAY, hal::gpio::gpiog::PG7>, >, - attenuator_spi: hal::spi::Spi, + attenuator_spi: hal::spi::Spi, adc1: hal::adc::Adc, adc2: hal::adc::Adc, adc1_in_p: hal::gpio::gpiof::PF11, From f56487401c8314cfc2b21512d3de8d008a25e63d Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Wed, 28 Oct 2020 16:14:48 +0100 Subject: [PATCH 07/12] Adding updates for PHY support --- src/main.rs | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/src/main.rs b/src/main.rs index c7d0eaa..58d879e 100644 --- a/src/main.rs +++ b/src/main.rs @@ -36,7 +36,7 @@ use embedded_hal::digital::v2::{InputPin, OutputPin}; use hal::{ dma::{DmaChannel, DmaExt, DmaInternal}, - ethernet, + ethernet::{self, PHY}, rcc::rec::ResetEnable, }; use smoltcp as net; @@ -183,7 +183,7 @@ const APP: () = { 'static, 'static, ethernet::EthernetDMA<'static>>, - eth_mac: ethernet::EthernetMAC, + eth_mac: ethernet::phy::LAN8742A, mac_addr: net::wire::EthernetAddress, pounder: Option>, @@ -690,6 +690,12 @@ const APP: () = { ) }; + // Reset and initialize the ethernet phy. + let mut lan8742a = + ethernet::phy::LAN8742A::new(eth_mac.set_phy_addr(0)); + lan8742a.phy_reset(); + lan8742a.phy_init(); + unsafe { ethernet::enable_interrupt() }; let store = unsafe { &mut NET_STORE }; @@ -708,7 +714,7 @@ const APP: () = { .ip_addrs(&mut store.ip_addrs[..]) .finalize(); - (interface, eth_mac) + (interface, lan8742a) }; cp.SCB.enable_icache(); From 20e9b6543c18611e91da2b15566ca720cd75c8f2 Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Tue, 3 Nov 2020 09:36:03 +0100 Subject: [PATCH 08/12] Adding WIP updates to using DMA --- Cargo.lock | 11 +- Cargo.toml | 4 +- openocd.gdb | 3 + src/main.rs | 292 +++++++++++++++++++++++----------------------------- 4 files changed, 143 insertions(+), 167 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index 998e749..915290b 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -185,6 +185,15 @@ dependencies = [ "cortex-m", ] +[[package]] +name = "embedded-dma" +version = "0.1.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "46c8c02e4347a0267ca60813c952017f4c5948c232474c6010a381a337f1bda4" +dependencies = [ + "stable_deref_trait", +] + [[package]] name = "embedded-hal" version = "0.2.4" @@ -558,12 +567,12 @@ dependencies = [ [[package]] name = "stm32h7xx-hal" version = "0.8.0" -source = "git+https://github.com/quartiq/stm32h7xx-hal?branch=rs/issue-158/managed-spi#cc36bbbaa1bf21e53732cfc0f3dd7175c3ed6d44" dependencies = [ "bare-metal 1.0.0", "cast", "cortex-m", "cortex-m-rt", + "embedded-dma", "embedded-hal", "nb 1.0.0", "paste 1.0.2", diff --git a/Cargo.toml b/Cargo.toml index 0f2df5c..0cac547 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -60,7 +60,7 @@ features = ["stm32h743v"] [dependencies.stm32h7xx-hal] features = ["stm32h743v", "rt", "unproven", "ethernet", "quadspi"] git = "https://github.com/quartiq/stm32h7xx-hal" -branch = "rs/issue-158/managed-spi" +branch = "feature/stabilizer-dma" [features] semihosting = ["panic-semihosting", "cortex-m-log/semihosting"] @@ -70,7 +70,7 @@ nightly = ["cortex-m/inline-asm"] [profile.dev] codegen-units = 1 incremental = false -opt-level = 3 +opt-level = 1 [profile.release] opt-level = 3 diff --git a/openocd.gdb b/openocd.gdb index e903a33..c1ae67a 100644 --- a/openocd.gdb +++ b/openocd.gdb @@ -26,3 +26,6 @@ set var $t0=*$cc continue end #set var $t0=*$cc + +source ../../PyCortexMDebug/cmdebug/svd_gdb.py +svd_load ~/Downloads/STM32H743x.svd diff --git a/src/main.rs b/src/main.rs index 58d879e..91058ba 100644 --- a/src/main.rs +++ b/src/main.rs @@ -35,9 +35,16 @@ use stm32h7xx_hal::prelude::*; use embedded_hal::digital::v2::{InputPin, OutputPin}; use hal::{ - dma::{DmaChannel, DmaExt, DmaInternal}, + dma::{ + Transfer, + PeripheralToMemory, MemoryToPeripheral, + traits::{Stream, TargetAddress}, + dma::{ + DmaConfig, + DMAReq, + }, + }, ethernet::{self, PHY}, - rcc::rec::ResetEnable, }; use smoltcp as net; @@ -46,12 +53,17 @@ use heapless::{consts::*, String}; #[link_section = ".sram3.eth"] static mut DES_RING: ethernet::DesRing = ethernet::DesRing::new(); +mod dac; +mod adc; mod afe; mod eeprom; mod iir; mod pounder; mod server; +use dac::{Dac0Output, Dac1Output}; +use adc::{Adc0Input, Adc1Input}; + #[cfg(not(feature = "semihosting"))] fn init_log() {} @@ -92,8 +104,6 @@ static mut NET_STORE: NetStorage = NetStorage { const SCALE: f32 = ((1 << 15) - 1) as f32; -const SPI_START: u32 = 0x00; - // static ETHERNET_PENDING: AtomicBool = AtomicBool::new(true); const TCP_RX_BUFFER_SIZE: usize = 8192; @@ -163,12 +173,12 @@ macro_rules! route_request { #[rtic::app(device = stm32h7xx_hal::stm32, peripherals = true, monotonic = rtic::cyccnt::CYCCNT)] const APP: () = { struct Resources { - adc0: hal::spi::Spi, - dac0: hal::spi::Spi, + adc0: Adc0Input, + dac0: Dac0Output, afe0: AFE0, - adc1: hal::spi::Spi, - dac1: hal::spi::Spi, + adc1: Adc1Input, + dac1: Dac1Output, afe1: AFE1, eeprom_i2c: hal::i2c::I2c, @@ -247,11 +257,10 @@ const APP: () = { afe::ProgrammableGainAmplifier::new(a0_pin, a1_pin) }; - ccdr.peripheral.DMA1.reset().enable(); - let mut dma_channels = dp.DMA1.split(); + let dma_streams = hal::dma::dma::StreamsTuple::new(dp.DMA1, ccdr.peripheral.DMA1); // Configure the SPI interfaces to the ADCs and DACs. - let adc0_spi = { + let adc0 = { let spi_miso = gpiob .pb14 .into_alternate_af5() @@ -273,33 +282,7 @@ const APP: () = { .suspend_when_inactive() .cs_delay(220e-9); - dma_channels.0.set_peripheral_address( - &dp.SPI2.txdr as *const _ as u32, - false, - ); - dma_channels - .0 - .set_memory_address(&SPI_START as *const _ as u32, false); - dma_channels - .0 - .set_direction(hal::dma::Direction::MemoryToPeripherial); - dma_channels.0.set_transfer_length(1); - dma_channels.0.cr().modify(|_, w| { - w.circ() - .enabled() - .psize() - .bits16() - .msize() - .bits16() - .pfctrl() - .dma() - }); - dma_channels.0.dmamux().modify(|_, w| { - w.dmareq_id() - .variant(hal::stm32::dmamux1::ccr::DMAREQ_ID_A::TIM2_UP) - }); - - let mut spi: hal::spi::Spi<_, _, u16> = dp.SPI2.spi( + let spi: hal::spi::Spi<_, _, u16> = dp.SPI2.spi( (spi_sck, spi_miso, hal::spi::NoMosi), config, 50.mhz(), @@ -307,16 +290,10 @@ const APP: () = { &ccdr.clocks, ); - // Kick-start the SPI transaction - we will add data to the TXFIFO to read from the ADC. - let spi_regs = unsafe { &*hal::stm32::SPI2::ptr() }; - spi_regs.cr1.modify(|_, w| w.cstart().started()); - - spi.listen(hal::spi::Event::Rxp); - - spi + Adc0Input::new(spi, dma_streams.0, dma_streams.1) }; - let adc1_spi = { + let adc1 = { let spi_miso = gpiob .pb4 .into_alternate_af6() @@ -338,33 +315,7 @@ const APP: () = { .suspend_when_inactive() .cs_delay(220e-9); - dma_channels.1.set_peripheral_address( - &dp.SPI3.txdr as *const _ as u32, - false, - ); - dma_channels - .1 - .set_memory_address(&SPI_START as *const _ as u32, false); - dma_channels - .1 - .set_direction(hal::dma::Direction::MemoryToPeripherial); - dma_channels.1.dmamux().modify(|_, w| { - w.dmareq_id() - .variant(hal::stm32::dmamux1::ccr::DMAREQ_ID_A::TIM2_UP) - }); - dma_channels.1.set_transfer_length(1); - dma_channels.1.cr().modify(|_, w| { - w.circ() - .enabled() - .psize() - .bits16() - .msize() - .bits16() - .pfctrl() - .dma() - }); - - let mut spi: hal::spi::Spi<_, _, u16> = dp.SPI3.spi( + let spi: hal::spi::Spi<_, _, u16> = dp.SPI3.spi( (spi_sck, spi_miso, hal::spi::NoMosi), config, 50.mhz(), @@ -372,12 +323,7 @@ const APP: () = { &ccdr.clocks, ); - let spi_regs = unsafe { &*hal::stm32::SPI3::ptr() }; - spi_regs.cr1.modify(|_, w| w.cstart().started()); - - spi.listen(hal::spi::Event::Rxp); - - spi + Adc1Input::new(spi, dma_streams.2, dma_streams.3) }; let _dac_clr_n = gpioe.pe12.into_push_pull_output().set_high().unwrap(); @@ -386,68 +332,76 @@ const APP: () = { let _dac1_ldac_n = gpioe.pe15.into_push_pull_output().set_low().unwrap(); - let dac0_spi = { - let spi_miso = gpioe - .pe5 - .into_alternate_af5() - .set_speed(hal::gpio::Speed::VeryHigh); - let spi_sck = gpioe - .pe2 - .into_alternate_af5() - .set_speed(hal::gpio::Speed::VeryHigh); - let _spi_nss = gpioe - .pe4 - .into_alternate_af5() - .set_speed(hal::gpio::Speed::VeryHigh); + let dac0 = { + let dac0_spi = { + let spi_miso = gpioe + .pe5 + .into_alternate_af5() + .set_speed(hal::gpio::Speed::VeryHigh); + let spi_sck = gpioe + .pe2 + .into_alternate_af5() + .set_speed(hal::gpio::Speed::VeryHigh); + let _spi_nss = gpioe + .pe4 + .into_alternate_af5() + .set_speed(hal::gpio::Speed::VeryHigh); - let config = hal::spi::Config::new(hal::spi::Mode { - polarity: hal::spi::Polarity::IdleHigh, - phase: hal::spi::Phase::CaptureOnSecondTransition, - }) - .manage_cs() - .suspend_when_inactive() - .communication_mode(hal::spi::CommunicationMode::Transmitter) - .swap_mosi_miso(); + let config = hal::spi::Config::new(hal::spi::Mode { + polarity: hal::spi::Polarity::IdleHigh, + phase: hal::spi::Phase::CaptureOnSecondTransition, + }) + .manage_cs() + .suspend_when_inactive() + .communication_mode(hal::spi::CommunicationMode::Transmitter) + .swap_mosi_miso(); - dp.SPI4.spi( - (spi_sck, spi_miso, hal::spi::NoMosi), - config, - 50.mhz(), - ccdr.peripheral.SPI4, - &ccdr.clocks, - ) + dp.SPI4.spi( + (spi_sck, spi_miso, hal::spi::NoMosi), + config, + 50.mhz(), + ccdr.peripheral.SPI4, + &ccdr.clocks, + ) + }; + + Dac0Output::new(dac0_spi) }; - let dac1_spi = { - let spi_miso = gpiof - .pf8 - .into_alternate_af5() - .set_speed(hal::gpio::Speed::VeryHigh); - let spi_sck = gpiof - .pf7 - .into_alternate_af5() - .set_speed(hal::gpio::Speed::VeryHigh); - let _spi_nss = gpiof - .pf6 - .into_alternate_af5() - .set_speed(hal::gpio::Speed::VeryHigh); + let dac1 = { + let dac1_spi = { + let spi_miso = gpiof + .pf8 + .into_alternate_af5() + .set_speed(hal::gpio::Speed::VeryHigh); + let spi_sck = gpiof + .pf7 + .into_alternate_af5() + .set_speed(hal::gpio::Speed::VeryHigh); + let _spi_nss = gpiof + .pf6 + .into_alternate_af5() + .set_speed(hal::gpio::Speed::VeryHigh); - let config = hal::spi::Config::new(hal::spi::Mode { - polarity: hal::spi::Polarity::IdleHigh, - phase: hal::spi::Phase::CaptureOnSecondTransition, - }) - .manage_cs() - .suspend_when_inactive() - .communication_mode(hal::spi::CommunicationMode::Transmitter) - .swap_mosi_miso(); + let config = hal::spi::Config::new(hal::spi::Mode { + polarity: hal::spi::Polarity::IdleHigh, + phase: hal::spi::Phase::CaptureOnSecondTransition, + }) + .manage_cs() + .communication_mode(hal::spi::CommunicationMode::Transmitter) + .suspend_when_inactive() + .swap_mosi_miso(); - dp.SPI5.spi( - (spi_sck, spi_miso, hal::spi::NoMosi), - config, - 50.mhz(), - ccdr.peripheral.SPI5, - &ccdr.clocks, - ) + dp.SPI5.spi( + (spi_sck, spi_miso, hal::spi::NoMosi), + config, + 50.mhz(), + ccdr.peripheral.SPI5, + &ccdr.clocks, + ) + }; + + Dac1Output::new(dac1_spi) }; let mut fp_led_0 = gpiod.pd5.into_push_pull_output(); @@ -728,24 +682,20 @@ const APP: () = { // Configure timer 2 to trigger conversions for the ADC let timer2 = - dp.TIM2.timer(500.khz(), ccdr.peripheral.TIM2, &ccdr.clocks); + dp.TIM2.timer(50.khz(), ccdr.peripheral.TIM2, &ccdr.clocks); { let t2_regs = unsafe { &*hal::stm32::TIM2::ptr() }; t2_regs.dier.modify(|_, w| w.ude().set_bit()); } - // Start the SPI transfers. - dma_channels.0.start(); - dma_channels.1.start(); - init::LateResources { afe0: afe0, - adc0: adc0_spi, - dac0: dac0_spi, + adc0: adc0, + dac0: dac0, afe1: afe1, - adc1: adc1_spi, - dac1: dac1_spi, + adc1: adc1, + dac1: dac1, timer: timer2, pounder: pounder_devices, @@ -757,30 +707,34 @@ const APP: () = { } } - #[task(binds = SPI3, resources = [adc1, dac1, iir_state, iir_ch], priority = 2)] - fn spi3(c: spi3::Context) { - let output: u16 = { - let a: u16 = c.resources.adc1.read().unwrap(); - let x0 = f32::from(a as i16); - let y0 = - c.resources.iir_ch[1].update(&mut c.resources.iir_state[1], x0); - y0 as i16 as u16 ^ 0x8000 - }; + #[task(binds=DMA1_STR3, resources=[adc1, dac1, iir_state, iir_ch], priority=2)] + fn adc1(c: adc1::Context) { + let samples = c.resources.adc1.transfer_complete_handler(); - c.resources.dac1.send(output).unwrap(); + let mut last_result: u16 = 0; + for sample in samples { + let x0 = f32::from(*sample as i16); + let y0 = c.resources.iir_ch[1].update(&mut c.resources.iir_state[1], x0); + last_result = y0 as i16 as u16 ^ 0x8000; + //c.resources.dac0.push(last_result); + } + + c.resources.dac1.write(last_result); } - #[task(binds = SPI2, resources = [adc0, dac0, iir_state, iir_ch], priority = 2)] - fn spi2(c: spi2::Context) { - let output: u16 = { - let a: u16 = c.resources.adc0.read().unwrap(); - let x0 = f32::from(a as i16); - let y0 = - c.resources.iir_ch[0].update(&mut c.resources.iir_state[0], x0); - y0 as i16 as u16 ^ 0x8000 - }; + #[task(binds=DMA1_STR1, resources=[adc0, dac0, iir_state, iir_ch], priority=2)] + fn adc0(c: adc0::Context) { + let samples = c.resources.adc0.transfer_complete_handler(); - c.resources.dac0.send(output).unwrap(); + let mut last_result: u16 = 0; + for sample in samples { + let x0 = f32::from(*sample as i16); + let y0 = c.resources.iir_ch[0].update(&mut c.resources.iir_state[0], x0); + last_result = y0 as i16 as u16 ^ 0x8000; + //c.resources.dac0.push(last_result); + } + + c.resources.dac0.write(last_result); } #[idle(resources=[net_interface, pounder, mac_addr, eth_mac, iir_state, iir_ch, afe0, afe1])] @@ -973,6 +927,16 @@ const APP: () = { unsafe { ethernet::interrupt_handler() } } + #[task(binds = SPI2, priority = 1)] + fn spi2(_: spi2::Context) { + panic!("ADC0 input overrun"); + } + + #[task(binds = SPI3, priority = 1)] + fn spi3(_: spi3::Context) { + panic!("ADC0 input overrun"); + } + extern "C" { // hw interrupt handlers for RTIC to use for scheduling tasks // one per priority From adaca88a50e11cd98899d0269f18e9ca8867eb57 Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Tue, 3 Nov 2020 09:41:14 +0100 Subject: [PATCH 09/12] Adding ADC/DAC modules --- src/adc.rs | 187 +++++++++++++++++++++++++++++++++++++++++++++++++++++ src/dac.rs | 64 ++++++++++++++++++ 2 files changed, 251 insertions(+) create mode 100644 src/adc.rs create mode 100644 src/dac.rs diff --git a/src/adc.rs b/src/adc.rs new file mode 100644 index 0000000..15d2f63 --- /dev/null +++ b/src/adc.rs @@ -0,0 +1,187 @@ +use super::{hal, DmaConfig, PeripheralToMemory, MemoryToPeripheral, TargetAddress, Transfer, DMAReq, +Stream}; + +const INPUT_BUFFER_SIZE: usize = 1; + +#[link_section = ".axisram.buffers"] +static mut SPI_START: [u16; 1] = [0x00]; + +#[link_section = ".axisram.buffers"] +static mut ADC0_BUF0: [u16; INPUT_BUFFER_SIZE] = [0; INPUT_BUFFER_SIZE]; + +#[link_section = ".axisram.buffers"] +static mut ADC0_BUF1: [u16; INPUT_BUFFER_SIZE] = [0; INPUT_BUFFER_SIZE]; + +#[link_section = ".axisram.buffers"] +static mut ADC1_BUF0: [u16; INPUT_BUFFER_SIZE] = [0; INPUT_BUFFER_SIZE]; + +#[link_section = ".axisram.buffers"] +static mut ADC1_BUF1: [u16; INPUT_BUFFER_SIZE] = [0; INPUT_BUFFER_SIZE]; + +struct SPI2 {} + +impl SPI2 { + pub fn new() -> Self { + Self {} + } +} + +unsafe impl TargetAddress for SPI2 { + type MemSize = u16; + + const REQUEST_LINE: Option = Some(DMAReq::TIM2_UP as u8); + + fn address(&self) -> u32 { + let regs = unsafe { &*hal::stm32::SPI2::ptr() }; + ®s.txdr as *const _ as u32 + } +} + +struct SPI3 {} + +impl SPI3 { + pub fn new() -> Self { + Self {} + } +} + +unsafe impl TargetAddress for SPI3 { + type MemSize = u16; + + const REQUEST_LINE: Option = Some(DMAReq::TIM2_UP as u8); + + fn address(&self) -> u32 { + let regs = unsafe { &*hal::stm32::SPI3::ptr() }; + ®s.txdr as *const _ as u32 + } +} + +pub struct Adc0Input { + next_buffer: Option<&'static mut [u16; INPUT_BUFFER_SIZE]>, + transfer: Transfer< + hal::dma::dma::Stream1, + hal::spi::Spi, + PeripheralToMemory, + &'static mut [u16; INPUT_BUFFER_SIZE]>, +} + +impl Adc0Input { + pub fn new( + spi: hal::spi::Spi, + trigger_stream: hal::dma::dma::Stream0, + data_stream: hal::dma::dma::Stream1, + ) -> Self { + let trigger_config = DmaConfig::default() + .memory_increment(false) + .peripheral_increment(false) + .circular_buffer(true); + + let mut trigger_transfer: Transfer<_, _, MemoryToPeripheral, _ > = Transfer::init( + trigger_stream, + &SPI2::new(), + unsafe { &mut SPI_START }, + None, + trigger_config); + + let data_config = DmaConfig::default() + .memory_increment(true) + .transfer_complete_interrupt(true) + .peripheral_increment(false); + + let mut spi = spi.disable(); + spi.listen(hal::spi::Event::Error); + + let mut data_transfer: Transfer<_, _, PeripheralToMemory, _ > = Transfer::init( + data_stream, + &spi, + unsafe { &mut ADC0_BUF0 }, + None, + data_config); + + spi.enable_dma_rx(); + spi.enable_dma_tx(); + + let spi = spi.enable(); + spi.inner().cr1.modify(|_, w| w.cstart().started()); + + data_transfer.start(); + trigger_transfer.start(); + + Self { + next_buffer: unsafe { Some(&mut ADC0_BUF1) }, + transfer: data_transfer, + } + } + + pub fn transfer_complete_handler(&mut self) -> &[u16; INPUT_BUFFER_SIZE] { + let next_buffer = self.next_buffer.take().unwrap(); + let (prev_buffer, _) = self.transfer.next_transfer(next_buffer).unwrap(); + self.next_buffer.replace(prev_buffer); + self.next_buffer.as_ref().unwrap() + } +} + +pub struct Adc1Input { + next_buffer: Option<&'static mut [u16; INPUT_BUFFER_SIZE]>, + transfer: Transfer< + hal::dma::dma::Stream3, + hal::spi::Spi, + PeripheralToMemory, + &'static mut [u16; INPUT_BUFFER_SIZE]>, +} + +impl Adc1Input { + pub fn new( + spi: hal::spi::Spi, + trigger_stream: hal::dma::dma::Stream2, + data_stream: hal::dma::dma::Stream3, + ) -> Self { + let trigger_config = DmaConfig::default() + .memory_increment(false) + .peripheral_increment(false) + .circular_buffer(true); + + let mut trigger_transfer: Transfer<_, _, MemoryToPeripheral, _ > = Transfer::init( + trigger_stream, + &SPI3::new(), + unsafe { &mut SPI_START }, + None, + trigger_config); + + let data_config = DmaConfig::default() + .memory_increment(true) + .transfer_complete_interrupt(true) + .peripheral_increment(false); + + let mut spi = spi.disable(); + spi.listen(hal::spi::Event::Error); + + let mut data_transfer: Transfer<_, _, PeripheralToMemory, _ > = Transfer::init( + data_stream, + &spi, + unsafe { &mut ADC1_BUF0 }, + None, + data_config); + + spi.enable_dma_rx(); + spi.enable_dma_tx(); + + let spi = spi.enable(); + spi.inner().cr1.modify(|_, w| w.cstart().started()); + + data_transfer.start(); + trigger_transfer.start(); + + Self { + next_buffer: unsafe { Some(&mut ADC1_BUF1) }, + transfer: data_transfer, + } + } + + pub fn transfer_complete_handler(&mut self) -> &[u16; INPUT_BUFFER_SIZE] { + let next_buffer = self.next_buffer.take().unwrap(); + let (prev_buffer, _) = self.transfer.next_transfer(next_buffer).unwrap(); + self.next_buffer.replace(prev_buffer); + self.next_buffer.as_ref().unwrap() + } +} diff --git a/src/dac.rs b/src/dac.rs new file mode 100644 index 0000000..fb5f4ab --- /dev/null +++ b/src/dac.rs @@ -0,0 +1,64 @@ + +use super::hal; +use heapless::consts; + +pub struct Dac0Output { + outputs: heapless::spsc::Queue, + spi: hal::spi::Spi, +} + +impl Dac0Output { + pub fn new(spi: hal::spi::Spi) -> Self { + spi.inner().cr1.modify(|_, w| w.cstart().started()); + Self { spi, outputs: heapless::spsc::Queue::new() } + } + + pub fn push(&mut self, value: u16) { + self.outputs.enqueue(value).unwrap(); + } + + pub fn update(&mut self) { + match self.outputs.dequeue() { + Some(value) => self.write(value), + None => {}, + } + } + + pub fn write(&mut self, value: u16) { + unsafe { + core::ptr::write_volatile(&self.spi.inner().txdr as *const _ as *mut u16, value); + } + } +} + +pub struct Dac1Output { + outputs: heapless::spsc::Queue, + spi: hal::spi::Spi, +} + +impl Dac1Output { + pub fn new( + spi: hal::spi::Spi, + ) -> Self { + spi.inner().cr1.modify(|_, w| w.cstart().started()); + + Self { spi, outputs: heapless::spsc::Queue::new() } + } + + pub fn push(&mut self, value: u16) { + self.outputs.enqueue(value).unwrap(); + } + + pub fn update(&mut self) { + match self.outputs.dequeue() { + Some(value) => self.write(value), + None => {}, + } + } + + pub fn write(&mut self, value: u16) { + unsafe { + core::ptr::write_volatile(&self.spi.inner().txdr as *const _ as *mut u16, value); + } + } +} From 4e5459433e2f16947abd2ce812e5c8b2ba5d867f Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Tue, 3 Nov 2020 09:41:45 +0100 Subject: [PATCH 10/12] Formatting --- Cargo.lock | 1 + src/adc.rs | 74 +++++++++++++++++++++++++++++++---------------------- src/dac.rs | 29 +++++++++++++++------ src/main.rs | 21 ++++++++------- 4 files changed, 76 insertions(+), 49 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index 915290b..ff768f0 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -567,6 +567,7 @@ dependencies = [ [[package]] name = "stm32h7xx-hal" version = "0.8.0" +source = "git+https://github.com/quartiq/stm32h7xx-hal?branch=feature/stabilizer-dma#5fbbfa9352f720994c210e5c21601f3acf9dc40c" dependencies = [ "bare-metal 1.0.0", "cast", diff --git a/src/adc.rs b/src/adc.rs index 15d2f63..dd006f1 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -1,5 +1,7 @@ -use super::{hal, DmaConfig, PeripheralToMemory, MemoryToPeripheral, TargetAddress, Transfer, DMAReq, -Stream}; +use super::{ + hal, DMAReq, DmaConfig, MemoryToPeripheral, PeripheralToMemory, Stream, + TargetAddress, Transfer, +}; const INPUT_BUFFER_SIZE: usize = 1; @@ -62,7 +64,8 @@ pub struct Adc0Input { hal::dma::dma::Stream1, hal::spi::Spi, PeripheralToMemory, - &'static mut [u16; INPUT_BUFFER_SIZE]>, + &'static mut [u16; INPUT_BUFFER_SIZE], + >, } impl Adc0Input { @@ -76,12 +79,14 @@ impl Adc0Input { .peripheral_increment(false) .circular_buffer(true); - let mut trigger_transfer: Transfer<_, _, MemoryToPeripheral, _ > = Transfer::init( - trigger_stream, - &SPI2::new(), - unsafe { &mut SPI_START }, - None, - trigger_config); + let mut trigger_transfer: Transfer<_, _, MemoryToPeripheral, _> = + Transfer::init( + trigger_stream, + &SPI2::new(), + unsafe { &mut SPI_START }, + None, + trigger_config, + ); let data_config = DmaConfig::default() .memory_increment(true) @@ -91,12 +96,14 @@ impl Adc0Input { let mut spi = spi.disable(); spi.listen(hal::spi::Event::Error); - let mut data_transfer: Transfer<_, _, PeripheralToMemory, _ > = Transfer::init( - data_stream, - &spi, - unsafe { &mut ADC0_BUF0 }, - None, - data_config); + let mut data_transfer: Transfer<_, _, PeripheralToMemory, _> = + Transfer::init( + data_stream, + &spi, + unsafe { &mut ADC0_BUF0 }, + None, + data_config, + ); spi.enable_dma_rx(); spi.enable_dma_tx(); @@ -115,7 +122,8 @@ impl Adc0Input { pub fn transfer_complete_handler(&mut self) -> &[u16; INPUT_BUFFER_SIZE] { let next_buffer = self.next_buffer.take().unwrap(); - let (prev_buffer, _) = self.transfer.next_transfer(next_buffer).unwrap(); + let (prev_buffer, _) = + self.transfer.next_transfer(next_buffer).unwrap(); self.next_buffer.replace(prev_buffer); self.next_buffer.as_ref().unwrap() } @@ -127,7 +135,8 @@ pub struct Adc1Input { hal::dma::dma::Stream3, hal::spi::Spi, PeripheralToMemory, - &'static mut [u16; INPUT_BUFFER_SIZE]>, + &'static mut [u16; INPUT_BUFFER_SIZE], + >, } impl Adc1Input { @@ -141,12 +150,14 @@ impl Adc1Input { .peripheral_increment(false) .circular_buffer(true); - let mut trigger_transfer: Transfer<_, _, MemoryToPeripheral, _ > = Transfer::init( - trigger_stream, - &SPI3::new(), - unsafe { &mut SPI_START }, - None, - trigger_config); + let mut trigger_transfer: Transfer<_, _, MemoryToPeripheral, _> = + Transfer::init( + trigger_stream, + &SPI3::new(), + unsafe { &mut SPI_START }, + None, + trigger_config, + ); let data_config = DmaConfig::default() .memory_increment(true) @@ -156,12 +167,14 @@ impl Adc1Input { let mut spi = spi.disable(); spi.listen(hal::spi::Event::Error); - let mut data_transfer: Transfer<_, _, PeripheralToMemory, _ > = Transfer::init( - data_stream, - &spi, - unsafe { &mut ADC1_BUF0 }, - None, - data_config); + let mut data_transfer: Transfer<_, _, PeripheralToMemory, _> = + Transfer::init( + data_stream, + &spi, + unsafe { &mut ADC1_BUF0 }, + None, + data_config, + ); spi.enable_dma_rx(); spi.enable_dma_tx(); @@ -180,7 +193,8 @@ impl Adc1Input { pub fn transfer_complete_handler(&mut self) -> &[u16; INPUT_BUFFER_SIZE] { let next_buffer = self.next_buffer.take().unwrap(); - let (prev_buffer, _) = self.transfer.next_transfer(next_buffer).unwrap(); + let (prev_buffer, _) = + self.transfer.next_transfer(next_buffer).unwrap(); self.next_buffer.replace(prev_buffer); self.next_buffer.as_ref().unwrap() } diff --git a/src/dac.rs b/src/dac.rs index fb5f4ab..575320d 100644 --- a/src/dac.rs +++ b/src/dac.rs @@ -1,4 +1,3 @@ - use super::hal; use heapless::consts; @@ -8,9 +7,14 @@ pub struct Dac0Output { } impl Dac0Output { - pub fn new(spi: hal::spi::Spi) -> Self { + pub fn new( + spi: hal::spi::Spi, + ) -> Self { spi.inner().cr1.modify(|_, w| w.cstart().started()); - Self { spi, outputs: heapless::spsc::Queue::new() } + Self { + spi, + outputs: heapless::spsc::Queue::new(), + } } pub fn push(&mut self, value: u16) { @@ -20,13 +24,16 @@ impl Dac0Output { pub fn update(&mut self) { match self.outputs.dequeue() { Some(value) => self.write(value), - None => {}, + None => {} } } pub fn write(&mut self, value: u16) { unsafe { - core::ptr::write_volatile(&self.spi.inner().txdr as *const _ as *mut u16, value); + core::ptr::write_volatile( + &self.spi.inner().txdr as *const _ as *mut u16, + value, + ); } } } @@ -42,7 +49,10 @@ impl Dac1Output { ) -> Self { spi.inner().cr1.modify(|_, w| w.cstart().started()); - Self { spi, outputs: heapless::spsc::Queue::new() } + Self { + spi, + outputs: heapless::spsc::Queue::new(), + } } pub fn push(&mut self, value: u16) { @@ -52,13 +62,16 @@ impl Dac1Output { pub fn update(&mut self) { match self.outputs.dequeue() { Some(value) => self.write(value), - None => {}, + None => {} } } pub fn write(&mut self, value: u16) { unsafe { - core::ptr::write_volatile(&self.spi.inner().txdr as *const _ as *mut u16, value); + core::ptr::write_volatile( + &self.spi.inner().txdr as *const _ as *mut u16, + value, + ); } } } diff --git a/src/main.rs b/src/main.rs index 91058ba..72d0db2 100644 --- a/src/main.rs +++ b/src/main.rs @@ -36,13 +36,9 @@ use embedded_hal::digital::v2::{InputPin, OutputPin}; use hal::{ dma::{ - Transfer, - PeripheralToMemory, MemoryToPeripheral, + dma::{DMAReq, DmaConfig}, traits::{Stream, TargetAddress}, - dma::{ - DmaConfig, - DMAReq, - }, + MemoryToPeripheral, PeripheralToMemory, Transfer, }, ethernet::{self, PHY}, }; @@ -53,16 +49,16 @@ use heapless::{consts::*, String}; #[link_section = ".sram3.eth"] static mut DES_RING: ethernet::DesRing = ethernet::DesRing::new(); -mod dac; mod adc; mod afe; +mod dac; mod eeprom; mod iir; mod pounder; mod server; -use dac::{Dac0Output, Dac1Output}; use adc::{Adc0Input, Adc1Input}; +use dac::{Dac0Output, Dac1Output}; #[cfg(not(feature = "semihosting"))] fn init_log() {} @@ -257,7 +253,8 @@ const APP: () = { afe::ProgrammableGainAmplifier::new(a0_pin, a1_pin) }; - let dma_streams = hal::dma::dma::StreamsTuple::new(dp.DMA1, ccdr.peripheral.DMA1); + let dma_streams = + hal::dma::dma::StreamsTuple::new(dp.DMA1, ccdr.peripheral.DMA1); // Configure the SPI interfaces to the ADCs and DACs. let adc0 = { @@ -714,7 +711,8 @@ const APP: () = { let mut last_result: u16 = 0; for sample in samples { let x0 = f32::from(*sample as i16); - let y0 = c.resources.iir_ch[1].update(&mut c.resources.iir_state[1], x0); + let y0 = + c.resources.iir_ch[1].update(&mut c.resources.iir_state[1], x0); last_result = y0 as i16 as u16 ^ 0x8000; //c.resources.dac0.push(last_result); } @@ -729,7 +727,8 @@ const APP: () = { let mut last_result: u16 = 0; for sample in samples { let x0 = f32::from(*sample as i16); - let y0 = c.resources.iir_ch[0].update(&mut c.resources.iir_state[0], x0); + let y0 = + c.resources.iir_ch[0].update(&mut c.resources.iir_state[0], x0); last_result = y0 as i16 as u16 ^ 0x8000; //c.resources.dac0.push(last_result); } From e95cad5bde8832c3fd2caf371f87e5d3c8d6f1e9 Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Tue, 3 Nov 2020 10:52:37 +0100 Subject: [PATCH 11/12] Adding WIP updates --- src/adc.rs | 5 ++--- src/dac.rs | 23 +++++++++++++++++++-- src/main.rs | 58 ++++++++++++++++++++++++++++++----------------------- 3 files changed, 56 insertions(+), 30 deletions(-) diff --git a/src/adc.rs b/src/adc.rs index dd006f1..9c3aa01 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -1,9 +1,8 @@ use super::{ - hal, DMAReq, DmaConfig, MemoryToPeripheral, PeripheralToMemory, Stream, - TargetAddress, Transfer, + hal, DMAReq, DmaConfig, MemoryToPeripheral, PeripheralToMemory, TargetAddress, Transfer, }; -const INPUT_BUFFER_SIZE: usize = 1; +const INPUT_BUFFER_SIZE: usize = 25; #[link_section = ".axisram.buffers"] static mut SPI_START: [u16; 1] = [0x00]; diff --git a/src/dac.rs b/src/dac.rs index 575320d..2c747ae 100644 --- a/src/dac.rs +++ b/src/dac.rs @@ -4,27 +4,37 @@ use heapless::consts; pub struct Dac0Output { outputs: heapless::spsc::Queue, spi: hal::spi::Spi, + timer: hal::timer::Timer, } impl Dac0Output { pub fn new( spi: hal::spi::Spi, + mut timer: hal::timer::Timer, ) -> Self { spi.inner().cr1.modify(|_, w| w.cstart().started()); + timer.pause(); + timer.reset_counter(); + timer.clear_irq(); + timer.listen(hal::timer::Event::TimeOut); + Self { spi, outputs: heapless::spsc::Queue::new(), + timer, } } pub fn push(&mut self, value: u16) { self.outputs.enqueue(value).unwrap(); + self.timer.resume(); } pub fn update(&mut self) { + self.timer.clear_irq(); match self.outputs.dequeue() { Some(value) => self.write(value), - None => {} + None => self.timer.pause(), } } @@ -41,28 +51,37 @@ impl Dac0Output { pub struct Dac1Output { outputs: heapless::spsc::Queue, spi: hal::spi::Spi, + timer: hal::timer::Timer, } impl Dac1Output { pub fn new( spi: hal::spi::Spi, + mut timer: hal::timer::Timer, ) -> Self { spi.inner().cr1.modify(|_, w| w.cstart().started()); + timer.pause(); + timer.reset_counter(); + timer.clear_irq(); + timer.listen(hal::timer::Event::TimeOut); Self { spi, outputs: heapless::spsc::Queue::new(), + timer, } } pub fn push(&mut self, value: u16) { self.outputs.enqueue(value).unwrap(); + self.timer.resume(); } pub fn update(&mut self) { + self.timer.clear_irq(); match self.outputs.dequeue() { Some(value) => self.write(value), - None => {} + None => self.timer.pause(), } } diff --git a/src/main.rs b/src/main.rs index 72d0db2..a314513 100644 --- a/src/main.rs +++ b/src/main.rs @@ -37,7 +37,7 @@ use embedded_hal::digital::v2::{InputPin, OutputPin}; use hal::{ dma::{ dma::{DMAReq, DmaConfig}, - traits::{Stream, TargetAddress}, + traits::TargetAddress, MemoryToPeripheral, PeripheralToMemory, Transfer, }, ethernet::{self, PHY}, @@ -46,6 +46,8 @@ use smoltcp as net; use heapless::{consts::*, String}; +const SAMPLE_FREQUENCY_KHZ: u32 = 800; + #[link_section = ".sram3.eth"] static mut DES_RING: ethernet::DesRing = ethernet::DesRing::new(); @@ -362,7 +364,8 @@ const APP: () = { ) }; - Dac0Output::new(dac0_spi) + let timer = dp.TIM3.timer(SAMPLE_FREQUENCY_KHZ.khz(), ccdr.peripheral.TIM3, &ccdr.clocks); + Dac0Output::new(dac0_spi, timer) }; let dac1 = { @@ -398,7 +401,8 @@ const APP: () = { ) }; - Dac1Output::new(dac1_spi) + let timer = dp.TIM4.timer(SAMPLE_FREQUENCY_KHZ.khz(), ccdr.peripheral.TIM4, &ccdr.clocks); + Dac1Output::new(dac1_spi, timer) }; let mut fp_led_0 = gpiod.pd5.into_push_pull_output(); @@ -679,7 +683,7 @@ const APP: () = { // Configure timer 2 to trigger conversions for the ADC let timer2 = - dp.TIM2.timer(50.khz(), ccdr.peripheral.TIM2, &ccdr.clocks); + dp.TIM2.timer(SAMPLE_FREQUENCY_KHZ.khz(), ccdr.peripheral.TIM2, &ccdr.clocks); { let t2_regs = unsafe { &*hal::stm32::TIM2::ptr() }; t2_regs.dier.modify(|_, w| w.ude().set_bit()); @@ -704,36 +708,30 @@ const APP: () = { } } - #[task(binds=DMA1_STR3, resources=[adc1, dac1, iir_state, iir_ch], priority=2)] - fn adc1(c: adc1::Context) { - let samples = c.resources.adc1.transfer_complete_handler(); - - let mut last_result: u16 = 0; - for sample in samples { - let x0 = f32::from(*sample as i16); - let y0 = - c.resources.iir_ch[1].update(&mut c.resources.iir_state[1], x0); - last_result = y0 as i16 as u16 ^ 0x8000; - //c.resources.dac0.push(last_result); - } - - c.resources.dac1.write(last_result); - } - #[task(binds=DMA1_STR1, resources=[adc0, dac0, iir_state, iir_ch], priority=2)] - fn adc0(c: adc0::Context) { + fn adc0(mut c: adc0::Context) { let samples = c.resources.adc0.transfer_complete_handler(); - let mut last_result: u16 = 0; for sample in samples { let x0 = f32::from(*sample as i16); let y0 = c.resources.iir_ch[0].update(&mut c.resources.iir_state[0], x0); - last_result = y0 as i16 as u16 ^ 0x8000; - //c.resources.dac0.push(last_result); + let result = y0 as i16 as u16 ^ 0x8000; + c.resources.dac0.lock(|dac| dac.push(result)); } + } - c.resources.dac0.write(last_result); + #[task(binds=DMA1_STR3, resources=[adc1, dac1, iir_state, iir_ch], priority=2)] + fn adc1(mut c: adc1::Context) { + let samples = c.resources.adc1.transfer_complete_handler(); + + for sample in samples { + let x0 = f32::from(*sample as i16); + let y0 = + c.resources.iir_ch[1].update(&mut c.resources.iir_state[1], x0); + let result = y0 as i16 as u16 ^ 0x8000; + c.resources.dac1.lock(|dac| dac.push(result)); + } } #[idle(resources=[net_interface, pounder, mac_addr, eth_mac, iir_state, iir_ch, afe0, afe1])] @@ -936,6 +934,16 @@ const APP: () = { panic!("ADC0 input overrun"); } + #[task(binds = TIM3, resources=[dac0], priority = 3)] + fn dac0(c: dac0::Context) { + c.resources.dac0.update(); + } + + #[task(binds = TIM4, resources=[dac1], priority = 3)] + fn dac1(c: dac1::Context) { + c.resources.dac1.update(); + } + extern "C" { // hw interrupt handlers for RTIC to use for scheduling tasks // one per priority From 5cc21cfde804b0713d9c34fb0d66fa8e4ee2916e Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Tue, 3 Nov 2020 16:09:00 +0100 Subject: [PATCH 12/12] Combining ADC + DAC ISRs --- src/adc.rs | 33 +++++++- src/dac.rs | 90 +++++++------------- src/iir.rs | 10 +++ src/main.rs | 232 +++++++++++++++++++++++++--------------------------- 4 files changed, 180 insertions(+), 185 deletions(-) diff --git a/src/adc.rs b/src/adc.rs index 9c3aa01..cb15c27 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -1,8 +1,9 @@ use super::{ - hal, DMAReq, DmaConfig, MemoryToPeripheral, PeripheralToMemory, TargetAddress, Transfer, + hal, DMAReq, DmaConfig, MemoryToPeripheral, PeripheralToMemory, Priority, + Stream, TargetAddress, Transfer, }; -const INPUT_BUFFER_SIZE: usize = 25; +const INPUT_BUFFER_SIZE: usize = 1; #[link_section = ".axisram.buffers"] static mut SPI_START: [u16; 1] = [0x00]; @@ -57,6 +58,25 @@ unsafe impl TargetAddress for SPI3 { } } +pub struct AdcInputs { + adc0: Adc0Input, + adc1: Adc1Input, +} + +impl AdcInputs { + pub fn new(adc0: Adc0Input, adc1: Adc1Input) -> Self { + Self { adc0, adc1 } + } + + pub fn transfer_complete_handler( + &mut self, + ) -> (&[u16; INPUT_BUFFER_SIZE], &[u16; INPUT_BUFFER_SIZE]) { + let adc0_buffer = self.adc0.transfer_complete_handler(); + let adc1_buffer = self.adc1.transfer_complete_handler(); + (adc0_buffer, adc1_buffer) + } +} + pub struct Adc0Input { next_buffer: Option<&'static mut [u16; INPUT_BUFFER_SIZE]>, transfer: Transfer< @@ -76,6 +96,7 @@ impl Adc0Input { let trigger_config = DmaConfig::default() .memory_increment(false) .peripheral_increment(false) + .priority(Priority::High) .circular_buffer(true); let mut trigger_transfer: Transfer<_, _, MemoryToPeripheral, _> = @@ -89,7 +110,7 @@ impl Adc0Input { let data_config = DmaConfig::default() .memory_increment(true) - .transfer_complete_interrupt(true) + .priority(Priority::VeryHigh) .peripheral_increment(false); let mut spi = spi.disable(); @@ -121,6 +142,8 @@ impl Adc0Input { pub fn transfer_complete_handler(&mut self) -> &[u16; INPUT_BUFFER_SIZE] { let next_buffer = self.next_buffer.take().unwrap(); + while hal::dma::dma::Stream1::::is_enabled() {} + self.transfer.clear_interrupts(); let (prev_buffer, _) = self.transfer.next_transfer(next_buffer).unwrap(); self.next_buffer.replace(prev_buffer); @@ -147,6 +170,7 @@ impl Adc1Input { let trigger_config = DmaConfig::default() .memory_increment(false) .peripheral_increment(false) + .priority(Priority::High) .circular_buffer(true); let mut trigger_transfer: Transfer<_, _, MemoryToPeripheral, _> = @@ -161,6 +185,7 @@ impl Adc1Input { let data_config = DmaConfig::default() .memory_increment(true) .transfer_complete_interrupt(true) + .priority(Priority::VeryHigh) .peripheral_increment(false); let mut spi = spi.disable(); @@ -192,6 +217,8 @@ impl Adc1Input { pub fn transfer_complete_handler(&mut self) -> &[u16; INPUT_BUFFER_SIZE] { let next_buffer = self.next_buffer.take().unwrap(); + while hal::dma::dma::Stream3::::is_enabled() {} + self.transfer.clear_interrupts(); let (prev_buffer, _) = self.transfer.next_transfer(next_buffer).unwrap(); self.next_buffer.replace(prev_buffer); diff --git a/src/dac.rs b/src/dac.rs index 2c747ae..d2b36a3 100644 --- a/src/dac.rs +++ b/src/dac.rs @@ -1,95 +1,61 @@ use super::hal; use heapless::consts; -pub struct Dac0Output { - outputs: heapless::spsc::Queue, - spi: hal::spi::Spi, +pub struct DacOutputs { + dac0_spi: hal::spi::Spi, + dac1_spi: hal::spi::Spi, + outputs: heapless::spsc::Queue<(u16, u16), consts::U32>, timer: hal::timer::Timer, } -impl Dac0Output { +impl DacOutputs { pub fn new( - spi: hal::spi::Spi, + dac0_spi: hal::spi::Spi, + dac1_spi: hal::spi::Spi, mut timer: hal::timer::Timer, ) -> Self { - spi.inner().cr1.modify(|_, w| w.cstart().started()); + dac0_spi.inner().cr1.modify(|_, w| w.cstart().started()); + dac1_spi.inner().cr1.modify(|_, w| w.cstart().started()); timer.pause(); timer.reset_counter(); timer.clear_irq(); timer.listen(hal::timer::Event::TimeOut); Self { - spi, + dac0_spi, + dac1_spi, outputs: heapless::spsc::Queue::new(), timer, } } - pub fn push(&mut self, value: u16) { - self.outputs.enqueue(value).unwrap(); + pub fn push(&mut self, dac0_value: u16, dac1_value: u16) { + self.outputs.enqueue((dac0_value, dac1_value)).unwrap(); self.timer.resume(); } pub fn update(&mut self) { self.timer.clear_irq(); match self.outputs.dequeue() { - Some(value) => self.write(value), - None => self.timer.pause(), - } + Some((dac0, dac1)) => self.write(dac0, dac1), + None => { + self.timer.pause(); + self.timer.reset_counter(); + self.timer.clear_irq(); + } + }; } - pub fn write(&mut self, value: u16) { + pub fn write(&mut self, dac0_value: u16, dac1_value: u16) { unsafe { core::ptr::write_volatile( - &self.spi.inner().txdr as *const _ as *mut u16, - value, - ); - } - } -} - -pub struct Dac1Output { - outputs: heapless::spsc::Queue, - spi: hal::spi::Spi, - timer: hal::timer::Timer, -} - -impl Dac1Output { - pub fn new( - spi: hal::spi::Spi, - mut timer: hal::timer::Timer, - ) -> Self { - spi.inner().cr1.modify(|_, w| w.cstart().started()); - timer.pause(); - timer.reset_counter(); - timer.clear_irq(); - timer.listen(hal::timer::Event::TimeOut); - - Self { - spi, - outputs: heapless::spsc::Queue::new(), - timer, - } - } - - pub fn push(&mut self, value: u16) { - self.outputs.enqueue(value).unwrap(); - self.timer.resume(); - } - - pub fn update(&mut self) { - self.timer.clear_irq(); - match self.outputs.dequeue() { - Some(value) => self.write(value), - None => self.timer.pause(), - } - } - - pub fn write(&mut self, value: u16) { - unsafe { - core::ptr::write_volatile( - &self.spi.inner().txdr as *const _ as *mut u16, - value, + &self.dac0_spi.inner().txdr as *const _ as *mut u16, + dac0_value, + ); + + core::ptr::write_volatile( + &self.dac1_spi.inner().txdr as *const _ as *mut u16, + dac1_value, ); } } diff --git a/src/iir.rs b/src/iir.rs index 0c34306..ff2d011 100644 --- a/src/iir.rs +++ b/src/iir.rs @@ -105,4 +105,14 @@ impl IIR { xy[xy.len() / 2] = y0; y0 } + + pub fn update_from_adc_sample( + &mut self, + sample: u16, + state: &mut IIRState, + ) -> u16 { + let x0 = f32::from(sample as i16); + let y0 = self.update(state, x0); + y0 as i16 as u16 ^ 0x8000 + } } diff --git a/src/main.rs b/src/main.rs index a314513..b176ca6 100644 --- a/src/main.rs +++ b/src/main.rs @@ -36,8 +36,9 @@ use embedded_hal::digital::v2::{InputPin, OutputPin}; use hal::{ dma::{ + config::Priority, dma::{DMAReq, DmaConfig}, - traits::TargetAddress, + traits::{Stream, TargetAddress}, MemoryToPeripheral, PeripheralToMemory, Transfer, }, ethernet::{self, PHY}, @@ -46,7 +47,7 @@ use smoltcp as net; use heapless::{consts::*, String}; -const SAMPLE_FREQUENCY_KHZ: u32 = 800; +const SAMPLE_FREQUENCY_KHZ: u32 = 500; #[link_section = ".sram3.eth"] static mut DES_RING: ethernet::DesRing = ethernet::DesRing::new(); @@ -59,8 +60,8 @@ mod iir; mod pounder; mod server; -use adc::{Adc0Input, Adc1Input}; -use dac::{Dac0Output, Dac1Output}; +use adc::{Adc0Input, Adc1Input, AdcInputs}; +use dac::DacOutputs; #[cfg(not(feature = "semihosting"))] fn init_log() {} @@ -171,14 +172,12 @@ macro_rules! route_request { #[rtic::app(device = stm32h7xx_hal::stm32, peripherals = true, monotonic = rtic::cyccnt::CYCCNT)] const APP: () = { struct Resources { - adc0: Adc0Input, - dac0: Dac0Output, afe0: AFE0, - - adc1: Adc1Input, - dac1: Dac1Output, afe1: AFE1, + adcs: AdcInputs, + dacs: DacOutputs, + eeprom_i2c: hal::i2c::I2c, timer: hal::timer::Timer, @@ -259,79 +258,84 @@ const APP: () = { hal::dma::dma::StreamsTuple::new(dp.DMA1, ccdr.peripheral.DMA1); // Configure the SPI interfaces to the ADCs and DACs. - let adc0 = { - let spi_miso = gpiob - .pb14 - .into_alternate_af5() - .set_speed(hal::gpio::Speed::VeryHigh); - let spi_sck = gpiob - .pb10 - .into_alternate_af5() - .set_speed(hal::gpio::Speed::VeryHigh); - let _spi_nss = gpiob - .pb9 - .into_alternate_af5() - .set_speed(hal::gpio::Speed::VeryHigh); + let adcs = { + let adc0 = { + let spi_miso = gpiob + .pb14 + .into_alternate_af5() + .set_speed(hal::gpio::Speed::VeryHigh); + let spi_sck = gpiob + .pb10 + .into_alternate_af5() + .set_speed(hal::gpio::Speed::VeryHigh); + let _spi_nss = gpiob + .pb9 + .into_alternate_af5() + .set_speed(hal::gpio::Speed::VeryHigh); - let config = hal::spi::Config::new(hal::spi::Mode { - polarity: hal::spi::Polarity::IdleHigh, - phase: hal::spi::Phase::CaptureOnSecondTransition, - }) - .manage_cs() - .suspend_when_inactive() - .cs_delay(220e-9); + let config = hal::spi::Config::new(hal::spi::Mode { + polarity: hal::spi::Polarity::IdleHigh, + phase: hal::spi::Phase::CaptureOnSecondTransition, + }) + .manage_cs() + .suspend_when_inactive() + .cs_delay(220e-9); - let spi: hal::spi::Spi<_, _, u16> = dp.SPI2.spi( - (spi_sck, spi_miso, hal::spi::NoMosi), - config, - 50.mhz(), - ccdr.peripheral.SPI2, - &ccdr.clocks, - ); + let spi: hal::spi::Spi<_, _, u16> = dp.SPI2.spi( + (spi_sck, spi_miso, hal::spi::NoMosi), + config, + 50.mhz(), + ccdr.peripheral.SPI2, + &ccdr.clocks, + ); - Adc0Input::new(spi, dma_streams.0, dma_streams.1) + Adc0Input::new(spi, dma_streams.0, dma_streams.1) + }; + + let adc1 = { + let spi_miso = gpiob + .pb4 + .into_alternate_af6() + .set_speed(hal::gpio::Speed::VeryHigh); + let spi_sck = gpioc + .pc10 + .into_alternate_af6() + .set_speed(hal::gpio::Speed::VeryHigh); + let _spi_nss = gpioa + .pa15 + .into_alternate_af6() + .set_speed(hal::gpio::Speed::VeryHigh); + + let config = hal::spi::Config::new(hal::spi::Mode { + polarity: hal::spi::Polarity::IdleHigh, + phase: hal::spi::Phase::CaptureOnSecondTransition, + }) + .manage_cs() + .suspend_when_inactive() + .cs_delay(220e-9); + + let spi: hal::spi::Spi<_, _, u16> = dp.SPI3.spi( + (spi_sck, spi_miso, hal::spi::NoMosi), + config, + 50.mhz(), + ccdr.peripheral.SPI3, + &ccdr.clocks, + ); + + Adc1Input::new(spi, dma_streams.2, dma_streams.3) + }; + + AdcInputs::new(adc0, adc1) }; - let adc1 = { - let spi_miso = gpiob - .pb4 - .into_alternate_af6() - .set_speed(hal::gpio::Speed::VeryHigh); - let spi_sck = gpioc - .pc10 - .into_alternate_af6() - .set_speed(hal::gpio::Speed::VeryHigh); - let _spi_nss = gpioa - .pa15 - .into_alternate_af6() - .set_speed(hal::gpio::Speed::VeryHigh); + let dacs = { + let _dac_clr_n = + gpioe.pe12.into_push_pull_output().set_high().unwrap(); + let _dac0_ldac_n = + gpioe.pe11.into_push_pull_output().set_low().unwrap(); + let _dac1_ldac_n = + gpioe.pe15.into_push_pull_output().set_low().unwrap(); - let config = hal::spi::Config::new(hal::spi::Mode { - polarity: hal::spi::Polarity::IdleHigh, - phase: hal::spi::Phase::CaptureOnSecondTransition, - }) - .manage_cs() - .suspend_when_inactive() - .cs_delay(220e-9); - - let spi: hal::spi::Spi<_, _, u16> = dp.SPI3.spi( - (spi_sck, spi_miso, hal::spi::NoMosi), - config, - 50.mhz(), - ccdr.peripheral.SPI3, - &ccdr.clocks, - ); - - Adc1Input::new(spi, dma_streams.2, dma_streams.3) - }; - - let _dac_clr_n = gpioe.pe12.into_push_pull_output().set_high().unwrap(); - let _dac0_ldac_n = - gpioe.pe11.into_push_pull_output().set_low().unwrap(); - let _dac1_ldac_n = - gpioe.pe15.into_push_pull_output().set_low().unwrap(); - - let dac0 = { let dac0_spi = { let spi_miso = gpioe .pe5 @@ -364,11 +368,6 @@ const APP: () = { ) }; - let timer = dp.TIM3.timer(SAMPLE_FREQUENCY_KHZ.khz(), ccdr.peripheral.TIM3, &ccdr.clocks); - Dac0Output::new(dac0_spi, timer) - }; - - let dac1 = { let dac1_spi = { let spi_miso = gpiof .pf8 @@ -401,8 +400,13 @@ const APP: () = { ) }; - let timer = dp.TIM4.timer(SAMPLE_FREQUENCY_KHZ.khz(), ccdr.peripheral.TIM4, &ccdr.clocks); - Dac1Output::new(dac1_spi, timer) + let timer = dp.TIM3.timer( + SAMPLE_FREQUENCY_KHZ.khz(), + ccdr.peripheral.TIM3, + &ccdr.clocks, + ); + + DacOutputs::new(dac0_spi, dac1_spi, timer) }; let mut fp_led_0 = gpiod.pd5.into_push_pull_output(); @@ -682,8 +686,11 @@ const APP: () = { cp.DWT.enable_cycle_counter(); // Configure timer 2 to trigger conversions for the ADC - let timer2 = - dp.TIM2.timer(SAMPLE_FREQUENCY_KHZ.khz(), ccdr.peripheral.TIM2, &ccdr.clocks); + let timer2 = dp.TIM2.timer( + SAMPLE_FREQUENCY_KHZ.khz(), + ccdr.peripheral.TIM2, + &ccdr.clocks, + ); { let t2_regs = unsafe { &*hal::stm32::TIM2::ptr() }; t2_regs.dier.modify(|_, w| w.ude().set_bit()); @@ -691,12 +698,10 @@ const APP: () = { init::LateResources { afe0: afe0, - adc0: adc0, - dac0: dac0, - afe1: afe1, - adc1: adc1, - dac1: dac1, + + adcs, + dacs, timer: timer2, pounder: pounder_devices, @@ -708,29 +713,26 @@ const APP: () = { } } - #[task(binds=DMA1_STR1, resources=[adc0, dac0, iir_state, iir_ch], priority=2)] - fn adc0(mut c: adc0::Context) { - let samples = c.resources.adc0.transfer_complete_handler(); - - for sample in samples { - let x0 = f32::from(*sample as i16); - let y0 = - c.resources.iir_ch[0].update(&mut c.resources.iir_state[0], x0); - let result = y0 as i16 as u16 ^ 0x8000; - c.resources.dac0.lock(|dac| dac.push(result)); - } + #[task(binds = TIM3, resources=[dacs], priority = 3)] + fn dac_update(c: dac_update::Context) { + c.resources.dacs.update(); } - #[task(binds=DMA1_STR3, resources=[adc1, dac1, iir_state, iir_ch], priority=2)] - fn adc1(mut c: adc1::Context) { - let samples = c.resources.adc1.transfer_complete_handler(); + #[task(binds=DMA1_STR3, resources=[adcs, dacs, iir_state, iir_ch], priority=2)] + fn adc_update(mut c: adc_update::Context) { + let (adc0_samples, adc1_samples) = + c.resources.adcs.transfer_complete_handler(); - for sample in samples { - let x0 = f32::from(*sample as i16); - let y0 = - c.resources.iir_ch[1].update(&mut c.resources.iir_state[1], x0); - let result = y0 as i16 as u16 ^ 0x8000; - c.resources.dac1.lock(|dac| dac.push(result)); + for (adc0, adc1) in adc0_samples.iter().zip(adc1_samples.iter()) { + let result_adc0 = c.resources.iir_ch[0] + .update_from_adc_sample(*adc0, &mut c.resources.iir_state[0]); + + let result_adc1 = c.resources.iir_ch[1] + .update_from_adc_sample(*adc1, &mut c.resources.iir_state[1]); + + c.resources + .dacs + .lock(|dacs| dacs.push(result_adc0, result_adc1)); } } @@ -934,16 +936,6 @@ const APP: () = { panic!("ADC0 input overrun"); } - #[task(binds = TIM3, resources=[dac0], priority = 3)] - fn dac0(c: dac0::Context) { - c.resources.dac0.update(); - } - - #[task(binds = TIM4, resources=[dac1], priority = 3)] - fn dac1(c: dac1::Context) { - c.resources.dac1.update(); - } - extern "C" { // hw interrupt handlers for RTIC to use for scheduling tasks // one per priority