diff --git a/Cargo.lock b/Cargo.lock index 56f8eed..ff768f0 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -10,21 +10,22 @@ dependencies = [ [[package]] name = "aligned" -version = "0.3.2" +version = "0.3.4" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "eb1ce8b3382016136ab1d31a1b5ce807144f8b7eb2d5f16b2108f0f07edceb94" +checksum = "c19796bd8d477f1a9d4ac2465b464a8b1359474f06a96bb3cda650b4fca309bf" dependencies = [ "as-slice", ] [[package]] name = "as-slice" -version = "0.1.3" +version = "0.1.4" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "37dfb65bc03b2bc85ee827004f14a6817e04160e3b1a28931986a666a9290e70" +checksum = "bb4d1c23475b74e3672afa8c2be22040b8b7783ad9b461021144ed10a46bb0e6" dependencies = [ "generic-array 0.12.3", "generic-array 0.13.2", + "generic-array 0.14.4", "stable_deref_trait", ] @@ -41,9 +42,9 @@ dependencies = [ [[package]] name = "autocfg" -version = "1.0.0" +version = "1.0.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "f8aac770f1885fd7e387acedd76065302551364496e46b3dd00860b2f8359b9d" +checksum = "cdb031dd78e28731d87d56cc8ffef4a8f36ca26c38fe2de700543e627f8a464a" [[package]] name = "bare-metal" @@ -55,10 +56,16 @@ dependencies = [ ] [[package]] -name = "bit_field" -version = "0.10.0" +name = "bare-metal" +version = "1.0.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "a165d606cf084741d4ac3a28fb6e9b1eb0bd31f6cd999098cfddb0b2ab381dc0" +checksum = "f8fe8f5a8a398345e52358e18ff07cc17a568fbca5c6f73873d3a62056309603" + +[[package]] +name = "bit_field" +version = "0.10.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "dcb6dd1c2376d2e096796e234a70e17e94cc2d5d54ff8ce42b28cef1d0d359a4" [[package]] name = "bitfield" @@ -101,12 +108,12 @@ checksum = "4785bdd1c96b2a846b2bd7cc02e86b6b3dbf14e7e53446c4f54c92a361040822" [[package]] name = "cortex-m" -version = "0.6.3" +version = "0.6.4" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "2be99930c99669a74d986f7fd2162085498b322e6daae8ef63a97cc9ac1dc73c" +checksum = "88cdafeafba636c00c467ded7f1587210725a1adfab0c24028a7844b87738263" dependencies = [ "aligned", - "bare-metal", + "bare-metal 0.2.5", "bitfield", "volatile-register", ] @@ -178,13 +185,22 @@ dependencies = [ "cortex-m", ] +[[package]] +name = "embedded-dma" +version = "0.1.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "46c8c02e4347a0267ca60813c952017f4c5948c232474c6010a381a337f1bda4" +dependencies = [ + "stable_deref_trait", +] + [[package]] name = "embedded-hal" version = "0.2.4" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "fa998ce59ec9765d15216393af37a58961ddcefb14c753b4816ba2191d865fcb" dependencies = [ - "nb 0.1.2", + "nb 0.1.3", "void", ] @@ -226,6 +242,16 @@ dependencies = [ "typenum", ] +[[package]] +name = "generic-array" +version = "0.14.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "501466ecc8a30d1d3b7fc9229b122b2ce8ed6e9d9223f1138d4babb253e51817" +dependencies = [ + "typenum", + "version_check", +] + [[package]] name = "hash32" version = "0.1.1" @@ -236,10 +262,16 @@ dependencies = [ ] [[package]] -name = "heapless" -version = "0.5.5" +name = "hashbrown" +version = "0.9.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "73a8a2391a3bc70b31f60e7a90daa5755a360559c0b6b9c5cfc0fee482362dc0" +checksum = "d7afe4a420e3fe79967a00898cc1f4db7c8a49a9333a29f8a4bd76a253d5cd04" + +[[package]] +name = "heapless" +version = "0.5.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "74911a68a1658cfcfb61bc0ccfbd536e3b6e906f8c2f7883ee50157e3e2184f1" dependencies = [ "as-slice", "generic-array 0.13.2", @@ -250,11 +282,12 @@ dependencies = [ [[package]] name = "indexmap" -version = "1.4.0" +version = "1.6.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "c398b2b113b55809ceb9ee3e753fcbac793f1956663f3c36549c1346015c2afe" +checksum = "55e2e4c765aa53a0424761bf9f41aa7a6ac1efa87238f59560640e27fca028f2" dependencies = [ "autocfg", + "hashbrown", ] [[package]] @@ -282,9 +315,12 @@ dependencies = [ [[package]] name = "nb" -version = "0.1.2" +version = "0.1.3" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "b1411551beb3c11dedfb0a90a0fa256b47d28b9ec2cdff34c25a2fa59e45dbdc" +checksum = "801d31da0513b6ec5214e9bf433a77966320625a37860f910be265be6e18d06f" +dependencies = [ + "nb 1.0.0", +] [[package]] name = "nb" @@ -300,9 +336,9 @@ checksum = "de96540e0ebde571dc55c73d60ef407c653844e6f9a1e2fdbd40c07b9252d812" [[package]] name = "panic-semihosting" -version = "0.5.3" +version = "0.5.4" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "c03864ac862876c16a308f5286f4aa217f1a69ac45df87ad3cd2847f818a642c" +checksum = "aed16eb761d0ee9161dd1319cb38c8007813b20f9720a5a682b283e7b8cdfe58" dependencies = [ "cortex-m", "cortex-m-semihosting", @@ -310,34 +346,40 @@ dependencies = [ [[package]] name = "paste" -version = "0.1.17" +version = "0.1.18" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "026c63fe245362be0322bfec5a9656d458d13f9cfb1785d1b38458b9968e8080" +checksum = "45ca20c77d80be666aef2b45486da86238fabe33e38306bd3118fe4af33fa880" dependencies = [ "paste-impl", "proc-macro-hack", ] [[package]] -name = "paste-impl" -version = "0.1.17" +name = "paste" +version = "1.0.2" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "7b9281a268ec213237dcd2aa3c3d0f46681b04ced37c1616fd36567a9e6954b0" +checksum = "ba7ae1a2180ed02ddfdb5ab70c70d596a26dd642e097bb6fe78b1bde8588ed97" + +[[package]] +name = "paste-impl" +version = "0.1.18" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d95a7db200b97ef370c8e6de0088252f7e0dfff7d047a28528e47456c0fc98b6" dependencies = [ "proc-macro-hack", ] [[package]] name = "proc-macro-hack" -version = "0.5.16" +version = "0.5.19" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "7e0456befd48169b9f13ef0f0ad46d492cf9d2dbb918bcf38e01eed4ce3ec5e4" +checksum = "dbf0c48bc1d91375ae5c3cd81e3722dff1abcf81a30960240640d223f59fe0e5" [[package]] name = "proc-macro2" -version = "1.0.18" +version = "1.0.24" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "beae6331a816b1f65d04c45b078fd8e6c93e8071771f41b8163255bbd8d7c8fa" +checksum = "1e0704ee1a7e00d7bb417d0770ea303c1bccbabf0ef1667dae92b5967f5f8a71" dependencies = [ "unicode-xid", ] @@ -400,9 +442,9 @@ checksum = "388a1df253eca08550bef6c72392cfe7c30914bf41df5269b68cbd6ff8f570a3" [[package]] name = "serde" -version = "1.0.115" +version = "1.0.117" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "e54c9a88f2da7238af84b5101443f0c0d0a3bbdc455e34a5c9497b1903ed55d5" +checksum = "b88fa983de7720629c9387e9f517353ed404164b1e482c970a90c1a4aaf7dc1a" dependencies = [ "serde_derive", ] @@ -419,9 +461,9 @@ dependencies = [ [[package]] name = "serde_derive" -version = "1.0.115" +version = "1.0.117" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "609feed1d0a73cc36a0182a840a9b37b4a82f0b1150369f0536a9e3f2a31dc48" +checksum = "cbd1ae72adb44aab48f325a02444a5fc079349a8d804c1fc922aed3f7454c74e" dependencies = [ "proc-macro2", "quote", @@ -462,14 +504,14 @@ dependencies = [ "serde-json-core", "smoltcp", "stm32h7-ethernet", - "stm32h7xx-hal 0.5.0", + "stm32h7xx-hal 0.8.0", ] [[package]] name = "stable_deref_trait" -version = "1.1.1" +version = "1.2.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "dba1a27d3efae4351c8051072d619e3ade2820635c3958d826bfea39d59b54c8" +checksum = "a8f112729512f8e442d81f95a8a7ddf2b7c6b8a1a6f509a95864142b30cab2d3" [[package]] name = "stm32h7" @@ -477,7 +519,18 @@ version = "0.11.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "e9beb5e2a223c82f263c3051bba4614aebc6e98bd40217df3cd8817c83ac7bd8" dependencies = [ - "bare-metal", + "bare-metal 0.2.5", + "cortex-m", + "vcell", +] + +[[package]] +name = "stm32h7" +version = "0.12.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7571f17d1ed7d67957d0004de6c52bd1ef5e736ed5ddc2bcecf001512269f77c" +dependencies = [ + "bare-metal 0.2.5", "cortex-m", "cortex-m-rt", "vcell", @@ -491,22 +544,7 @@ dependencies = [ "cortex-m", "log", "smoltcp", - "stm32h7xx-hal 0.5.0 (registry+https://github.com/rust-lang/crates.io-index)", -] - -[[package]] -name = "stm32h7xx-hal" -version = "0.5.0" -dependencies = [ - "bare-metal", - "cast", - "cortex-m", - "cortex-m-rt", - "embedded-hal", - "nb 0.1.2", - "paste", - "stm32h7", - "void", + "stm32h7xx-hal 0.5.0", ] [[package]] @@ -515,22 +553,40 @@ version = "0.5.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "987c66628f30012ed9a41cc738421c5caece03292c0cc8fd1e99956f122735bd" dependencies = [ - "bare-metal", + "bare-metal 0.2.5", "cast", "cortex-m", "cortex-m-rt", "embedded-hal", - "nb 0.1.2", - "paste", - "stm32h7", + "nb 0.1.3", + "paste 0.1.18", + "stm32h7 0.11.0", + "void", +] + +[[package]] +name = "stm32h7xx-hal" +version = "0.8.0" +source = "git+https://github.com/quartiq/stm32h7xx-hal?branch=feature/stabilizer-dma#5fbbfa9352f720994c210e5c21601f3acf9dc40c" +dependencies = [ + "bare-metal 1.0.0", + "cast", + "cortex-m", + "cortex-m-rt", + "embedded-dma", + "embedded-hal", + "nb 1.0.0", + "paste 1.0.2", + "smoltcp", + "stm32h7 0.12.1", "void", ] [[package]] name = "syn" -version = "1.0.33" +version = "1.0.48" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "e8d5d96e8cbb005d6959f119f773bfaebb5684296108fb32600c00cde305b2cd" +checksum = "cc371affeffc477f42a221a1e4297aedcea33d47d19b61455588bd9d8f6b19ac" dependencies = [ "proc-macro2", "quote", @@ -545,9 +601,9 @@ checksum = "373c8a200f9e67a0c95e62a4f52fbf80c23b4381c05a17845531982fa99e6b33" [[package]] name = "unicode-xid" -version = "0.2.0" +version = "0.2.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "826e7639553986605ec5979c7dd957c7895e93eabed50ab2ffa7f6128a75097c" +checksum = "f7fe0bb3479651439c9112f72b6c505038574c9fbb575ed1bf3b797fa39dd564" [[package]] name = "vcell" diff --git a/Cargo.toml b/Cargo.toml index 578420e..0cac547 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -58,10 +58,9 @@ branch = "master" features = ["stm32h743v"] [dependencies.stm32h7xx-hal] -features = ["stm32h743v", "rt", "unproven"] -# git = "https://github.com/quartiq/stm32h7xx-hal.git" -# branch = "feature/pounder-support" -path = "../stm32h7xx-hal" +features = ["stm32h743v", "rt", "unproven", "ethernet", "quadspi"] +git = "https://github.com/quartiq/stm32h7xx-hal" +branch = "feature/stabilizer-dma" [features] semihosting = ["panic-semihosting", "cortex-m-log/semihosting"] @@ -71,7 +70,7 @@ nightly = ["cortex-m/inline-asm"] [profile.dev] codegen-units = 1 incremental = false -opt-level = 3 +opt-level = 1 [profile.release] opt-level = 3 diff --git a/openocd.gdb b/openocd.gdb index e903a33..c1ae67a 100644 --- a/openocd.gdb +++ b/openocd.gdb @@ -26,3 +26,6 @@ set var $t0=*$cc continue end #set var $t0=*$cc + +source ../../PyCortexMDebug/cmdebug/svd_gdb.py +svd_load ~/Downloads/STM32H743x.svd diff --git a/src/adc.rs b/src/adc.rs new file mode 100644 index 0000000..cb15c27 --- /dev/null +++ b/src/adc.rs @@ -0,0 +1,227 @@ +use super::{ + hal, DMAReq, DmaConfig, MemoryToPeripheral, PeripheralToMemory, Priority, + Stream, TargetAddress, Transfer, +}; + +const INPUT_BUFFER_SIZE: usize = 1; + +#[link_section = ".axisram.buffers"] +static mut SPI_START: [u16; 1] = [0x00]; + +#[link_section = ".axisram.buffers"] +static mut ADC0_BUF0: [u16; INPUT_BUFFER_SIZE] = [0; INPUT_BUFFER_SIZE]; + +#[link_section = ".axisram.buffers"] +static mut ADC0_BUF1: [u16; INPUT_BUFFER_SIZE] = [0; INPUT_BUFFER_SIZE]; + +#[link_section = ".axisram.buffers"] +static mut ADC1_BUF0: [u16; INPUT_BUFFER_SIZE] = [0; INPUT_BUFFER_SIZE]; + +#[link_section = ".axisram.buffers"] +static mut ADC1_BUF1: [u16; INPUT_BUFFER_SIZE] = [0; INPUT_BUFFER_SIZE]; + +struct SPI2 {} + +impl SPI2 { + pub fn new() -> Self { + Self {} + } +} + +unsafe impl TargetAddress for SPI2 { + type MemSize = u16; + + const REQUEST_LINE: Option = Some(DMAReq::TIM2_UP as u8); + + fn address(&self) -> u32 { + let regs = unsafe { &*hal::stm32::SPI2::ptr() }; + ®s.txdr as *const _ as u32 + } +} + +struct SPI3 {} + +impl SPI3 { + pub fn new() -> Self { + Self {} + } +} + +unsafe impl TargetAddress for SPI3 { + type MemSize = u16; + + const REQUEST_LINE: Option = Some(DMAReq::TIM2_UP as u8); + + fn address(&self) -> u32 { + let regs = unsafe { &*hal::stm32::SPI3::ptr() }; + ®s.txdr as *const _ as u32 + } +} + +pub struct AdcInputs { + adc0: Adc0Input, + adc1: Adc1Input, +} + +impl AdcInputs { + pub fn new(adc0: Adc0Input, adc1: Adc1Input) -> Self { + Self { adc0, adc1 } + } + + pub fn transfer_complete_handler( + &mut self, + ) -> (&[u16; INPUT_BUFFER_SIZE], &[u16; INPUT_BUFFER_SIZE]) { + let adc0_buffer = self.adc0.transfer_complete_handler(); + let adc1_buffer = self.adc1.transfer_complete_handler(); + (adc0_buffer, adc1_buffer) + } +} + +pub struct Adc0Input { + next_buffer: Option<&'static mut [u16; INPUT_BUFFER_SIZE]>, + transfer: Transfer< + hal::dma::dma::Stream1, + hal::spi::Spi, + PeripheralToMemory, + &'static mut [u16; INPUT_BUFFER_SIZE], + >, +} + +impl Adc0Input { + pub fn new( + spi: hal::spi::Spi, + trigger_stream: hal::dma::dma::Stream0, + data_stream: hal::dma::dma::Stream1, + ) -> Self { + let trigger_config = DmaConfig::default() + .memory_increment(false) + .peripheral_increment(false) + .priority(Priority::High) + .circular_buffer(true); + + let mut trigger_transfer: Transfer<_, _, MemoryToPeripheral, _> = + Transfer::init( + trigger_stream, + &SPI2::new(), + unsafe { &mut SPI_START }, + None, + trigger_config, + ); + + let data_config = DmaConfig::default() + .memory_increment(true) + .priority(Priority::VeryHigh) + .peripheral_increment(false); + + let mut spi = spi.disable(); + spi.listen(hal::spi::Event::Error); + + let mut data_transfer: Transfer<_, _, PeripheralToMemory, _> = + Transfer::init( + data_stream, + &spi, + unsafe { &mut ADC0_BUF0 }, + None, + data_config, + ); + + spi.enable_dma_rx(); + spi.enable_dma_tx(); + + let spi = spi.enable(); + spi.inner().cr1.modify(|_, w| w.cstart().started()); + + data_transfer.start(); + trigger_transfer.start(); + + Self { + next_buffer: unsafe { Some(&mut ADC0_BUF1) }, + transfer: data_transfer, + } + } + + pub fn transfer_complete_handler(&mut self) -> &[u16; INPUT_BUFFER_SIZE] { + let next_buffer = self.next_buffer.take().unwrap(); + while hal::dma::dma::Stream1::::is_enabled() {} + self.transfer.clear_interrupts(); + let (prev_buffer, _) = + self.transfer.next_transfer(next_buffer).unwrap(); + self.next_buffer.replace(prev_buffer); + self.next_buffer.as_ref().unwrap() + } +} + +pub struct Adc1Input { + next_buffer: Option<&'static mut [u16; INPUT_BUFFER_SIZE]>, + transfer: Transfer< + hal::dma::dma::Stream3, + hal::spi::Spi, + PeripheralToMemory, + &'static mut [u16; INPUT_BUFFER_SIZE], + >, +} + +impl Adc1Input { + pub fn new( + spi: hal::spi::Spi, + trigger_stream: hal::dma::dma::Stream2, + data_stream: hal::dma::dma::Stream3, + ) -> Self { + let trigger_config = DmaConfig::default() + .memory_increment(false) + .peripheral_increment(false) + .priority(Priority::High) + .circular_buffer(true); + + let mut trigger_transfer: Transfer<_, _, MemoryToPeripheral, _> = + Transfer::init( + trigger_stream, + &SPI3::new(), + unsafe { &mut SPI_START }, + None, + trigger_config, + ); + + let data_config = DmaConfig::default() + .memory_increment(true) + .transfer_complete_interrupt(true) + .priority(Priority::VeryHigh) + .peripheral_increment(false); + + let mut spi = spi.disable(); + spi.listen(hal::spi::Event::Error); + + let mut data_transfer: Transfer<_, _, PeripheralToMemory, _> = + Transfer::init( + data_stream, + &spi, + unsafe { &mut ADC1_BUF0 }, + None, + data_config, + ); + + spi.enable_dma_rx(); + spi.enable_dma_tx(); + + let spi = spi.enable(); + spi.inner().cr1.modify(|_, w| w.cstart().started()); + + data_transfer.start(); + trigger_transfer.start(); + + Self { + next_buffer: unsafe { Some(&mut ADC1_BUF1) }, + transfer: data_transfer, + } + } + + pub fn transfer_complete_handler(&mut self) -> &[u16; INPUT_BUFFER_SIZE] { + let next_buffer = self.next_buffer.take().unwrap(); + while hal::dma::dma::Stream3::::is_enabled() {} + self.transfer.clear_interrupts(); + let (prev_buffer, _) = + self.transfer.next_transfer(next_buffer).unwrap(); + self.next_buffer.replace(prev_buffer); + self.next_buffer.as_ref().unwrap() + } +} diff --git a/src/dac.rs b/src/dac.rs new file mode 100644 index 0000000..d2b36a3 --- /dev/null +++ b/src/dac.rs @@ -0,0 +1,62 @@ +use super::hal; +use heapless::consts; + +pub struct DacOutputs { + dac0_spi: hal::spi::Spi, + dac1_spi: hal::spi::Spi, + outputs: heapless::spsc::Queue<(u16, u16), consts::U32>, + timer: hal::timer::Timer, +} + +impl DacOutputs { + pub fn new( + dac0_spi: hal::spi::Spi, + dac1_spi: hal::spi::Spi, + mut timer: hal::timer::Timer, + ) -> Self { + dac0_spi.inner().cr1.modify(|_, w| w.cstart().started()); + dac1_spi.inner().cr1.modify(|_, w| w.cstart().started()); + timer.pause(); + timer.reset_counter(); + timer.clear_irq(); + timer.listen(hal::timer::Event::TimeOut); + + Self { + dac0_spi, + dac1_spi, + outputs: heapless::spsc::Queue::new(), + timer, + } + } + + pub fn push(&mut self, dac0_value: u16, dac1_value: u16) { + self.outputs.enqueue((dac0_value, dac1_value)).unwrap(); + self.timer.resume(); + } + + pub fn update(&mut self) { + self.timer.clear_irq(); + match self.outputs.dequeue() { + Some((dac0, dac1)) => self.write(dac0, dac1), + None => { + self.timer.pause(); + self.timer.reset_counter(); + self.timer.clear_irq(); + } + }; + } + + pub fn write(&mut self, dac0_value: u16, dac1_value: u16) { + unsafe { + core::ptr::write_volatile( + &self.dac0_spi.inner().txdr as *const _ as *mut u16, + dac0_value, + ); + + core::ptr::write_volatile( + &self.dac1_spi.inner().txdr as *const _ as *mut u16, + dac1_value, + ); + } + } +} diff --git a/src/iir.rs b/src/iir.rs index 0c34306..ff2d011 100644 --- a/src/iir.rs +++ b/src/iir.rs @@ -105,4 +105,14 @@ impl IIR { xy[xy.len() / 2] = y0; y0 } + + pub fn update_from_adc_sample( + &mut self, + sample: u16, + state: &mut IIRState, + ) -> u16 { + let x0 = f32::from(sample as i16); + let y0 = self.update(state, x0); + y0 as i16 as u16 ^ 0x8000 + } } diff --git a/src/main.rs b/src/main.rs index db0558a..565c8b3 100644 --- a/src/main.rs +++ b/src/main.rs @@ -1,4 +1,3 @@ -#![deny(warnings)] #![allow(clippy::missing_safety_doc)] #![no_std] #![no_main] @@ -35,21 +34,36 @@ use stm32h7xx_hal::prelude::*; use embedded_hal::digital::v2::{InputPin, OutputPin}; +use hal::{ + dma::{ + config::Priority, + dma::{DMAReq, DmaConfig}, + traits::{Stream, TargetAddress}, + MemoryToPeripheral, PeripheralToMemory, Transfer, + }, + ethernet::{self, PHY}, +}; use smoltcp as net; -use stm32h7_ethernet as ethernet; use heapless::{consts::*, String}; +const SAMPLE_FREQUENCY_KHZ: u32 = 500; + #[link_section = ".sram3.eth"] static mut DES_RING: ethernet::DesRing = ethernet::DesRing::new(); +mod adc; mod afe; +mod dac; mod eeprom; mod hrtimer; mod iir; mod pounder; mod server; +use adc::{Adc0Input, Adc1Input, AdcInputs}; +use dac::DacOutputs; + #[cfg(not(feature = "semihosting"))] fn init_log() {} @@ -90,8 +104,6 @@ static mut NET_STORE: NetStorage = NetStorage { const SCALE: f32 = ((1 << 15) - 1) as f32; -const SPI_START_CODE: u32 = 0x201; - // static ETHERNET_PENDING: AtomicBool = AtomicBool::new(true); const TCP_RX_BUFFER_SIZE: usize = 8192; @@ -161,36 +173,25 @@ macro_rules! route_request { #[rtic::app(device = stm32h7xx_hal::stm32, peripherals = true, monotonic = rtic::cyccnt::CYCCNT)] const APP: () = { struct Resources { - adc0: hal::spi::Spi, - dac0: hal::spi::Spi, afe0: AFE0, - - adc1: hal::spi::Spi, - dac1: hal::spi::Spi, afe1: AFE1, + adcs: AdcInputs, + dacs: DacOutputs, + eeprom_i2c: hal::i2c::I2c, timer: hal::timer::Timer, // Note: It appears that rustfmt generates a format that GDB cannot recognize, which - // results in GDB breakpoints being set improperly. To debug, redefine the following - // definition to: - // - // ```rust - // net_interface: net::iface::EthernetInterface< - // 'static, - // 'static, - // 'static, - // ethernet::EthernetDMA<'static>>, - // ``` + // results in GDB breakpoints being set improperly. + #[rustfmt::skip] net_interface: net::iface::EthernetInterface< 'static, 'static, 'static, - ethernet::EthernetDMA<'static>, - >, - eth_mac: ethernet::EthernetMAC, + ethernet::EthernetDMA<'static>>, + eth_mac: ethernet::phy::LAN8742A, mac_addr: net::wire::EthernetAddress, pounder: Option, @@ -209,8 +210,19 @@ const APP: () = { let pwr = dp.PWR.constrain(); let vos = pwr.freeze(); + // Enable SRAM3 for the ethernet descriptor ring. + dp.RCC.ahb2enr.modify(|_, w| w.sram3en().set_bit()); + + // Clear reset flags. + dp.RCC.rsr.write(|w| w.rmvf().set_bit()); + + // Select the PLLs for SPI. + dp.RCC + .d2ccip1r + .modify(|_, w| w.spi123sel().pll2_p().spi45sel().pll2_q()); + let rcc = dp.RCC.constrain(); - let mut clocks = rcc + let ccdr = rcc .use_hse(8.mhz()) .sysclk(400.mhz()) .hclk(200.mhz()) @@ -221,25 +233,15 @@ const APP: () = { init_log(); - // Enable SRAM3 for the ethernet descriptor ring. - clocks.rb.ahb2enr.modify(|_, w| w.sram3en().set_bit()); + let mut delay = hal::delay::Delay::new(cp.SYST, ccdr.clocks); - clocks.rb.rsr.write(|w| w.rmvf().set_bit()); - - clocks - .rb - .d2ccip1r - .modify(|_, w| w.spi123sel().pll2_p().spi45sel().pll2_q()); - - let mut delay = hal::delay::Delay::new(cp.SYST, clocks.clocks); - - let gpioa = dp.GPIOA.split(&mut clocks); - let gpiob = dp.GPIOB.split(&mut clocks); - let gpioc = dp.GPIOC.split(&mut clocks); - let gpiod = dp.GPIOD.split(&mut clocks); - let gpioe = dp.GPIOE.split(&mut clocks); - let gpiof = dp.GPIOF.split(&mut clocks); - let gpiog = dp.GPIOG.split(&mut clocks); + let gpioa = dp.GPIOA.split(ccdr.peripheral.GPIOA); + let gpiob = dp.GPIOB.split(ccdr.peripheral.GPIOB); + let gpioc = dp.GPIOC.split(ccdr.peripheral.GPIOC); + let gpiod = dp.GPIOD.split(ccdr.peripheral.GPIOD); + let gpioe = dp.GPIOE.split(ccdr.peripheral.GPIOE); + let gpiof = dp.GPIOF.split(ccdr.peripheral.GPIOF); + let gpiog = dp.GPIOG.split(ccdr.peripheral.GPIOG); let afe0 = { let a0_pin = gpiof.pf2.into_push_pull_output(); @@ -253,147 +255,159 @@ const APP: () = { afe::ProgrammableGainAmplifier::new(a0_pin, a1_pin) }; + let dma_streams = + hal::dma::dma::StreamsTuple::new(dp.DMA1, ccdr.peripheral.DMA1); + // Configure the SPI interfaces to the ADCs and DACs. - let adc0_spi = { - let spi_miso = gpiob - .pb14 - .into_alternate_af5() - .set_speed(hal::gpio::Speed::VeryHigh); - let spi_sck = gpiob - .pb10 - .into_alternate_af5() - .set_speed(hal::gpio::Speed::VeryHigh); - let _spi_nss = gpiob - .pb9 - .into_alternate_af5() - .set_speed(hal::gpio::Speed::VeryHigh); + let adcs = { + let adc0 = { + let spi_miso = gpiob + .pb14 + .into_alternate_af5() + .set_speed(hal::gpio::Speed::VeryHigh); + let spi_sck = gpiob + .pb10 + .into_alternate_af5() + .set_speed(hal::gpio::Speed::VeryHigh); + let _spi_nss = gpiob + .pb9 + .into_alternate_af5() + .set_speed(hal::gpio::Speed::VeryHigh); - let config = hal::spi::Config::new(hal::spi::Mode { - polarity: hal::spi::Polarity::IdleHigh, - phase: hal::spi::Phase::CaptureOnSecondTransition, - }) - .communication_mode(hal::spi::CommunicationMode::Receiver) - .manage_cs() - .transfer_size(1) - .frame_size(16) - .cs_delay(220e-9); + let config = hal::spi::Config::new(hal::spi::Mode { + polarity: hal::spi::Polarity::IdleHigh, + phase: hal::spi::Phase::CaptureOnSecondTransition, + }) + .manage_cs() + .suspend_when_inactive() + .cs_delay(220e-9); - let mut spi = dp.SPI2.spi( - (spi_sck, spi_miso, hal::spi::NoMosi), - config, - 50.mhz(), - &clocks, + let spi: hal::spi::Spi<_, _, u16> = dp.SPI2.spi( + (spi_sck, spi_miso, hal::spi::NoMosi), + config, + 50.mhz(), + ccdr.peripheral.SPI2, + &ccdr.clocks, + ); + + Adc0Input::new(spi, dma_streams.0, dma_streams.1) + }; + + let adc1 = { + let spi_miso = gpiob + .pb4 + .into_alternate_af6() + .set_speed(hal::gpio::Speed::VeryHigh); + let spi_sck = gpioc + .pc10 + .into_alternate_af6() + .set_speed(hal::gpio::Speed::VeryHigh); + let _spi_nss = gpioa + .pa15 + .into_alternate_af6() + .set_speed(hal::gpio::Speed::VeryHigh); + + let config = hal::spi::Config::new(hal::spi::Mode { + polarity: hal::spi::Polarity::IdleHigh, + phase: hal::spi::Phase::CaptureOnSecondTransition, + }) + .manage_cs() + .suspend_when_inactive() + .cs_delay(220e-9); + + let spi: hal::spi::Spi<_, _, u16> = dp.SPI3.spi( + (spi_sck, spi_miso, hal::spi::NoMosi), + config, + 50.mhz(), + ccdr.peripheral.SPI3, + &ccdr.clocks, + ); + + Adc1Input::new(spi, dma_streams.2, dma_streams.3) + }; + + AdcInputs::new(adc0, adc1) + }; + + let dacs = { + let _dac_clr_n = + gpioe.pe12.into_push_pull_output().set_high().unwrap(); + let _dac0_ldac_n = + gpioe.pe11.into_push_pull_output().set_low().unwrap(); + let _dac1_ldac_n = + gpioe.pe15.into_push_pull_output().set_low().unwrap(); + + let dac0_spi = { + let spi_miso = gpioe + .pe5 + .into_alternate_af5() + .set_speed(hal::gpio::Speed::VeryHigh); + let spi_sck = gpioe + .pe2 + .into_alternate_af5() + .set_speed(hal::gpio::Speed::VeryHigh); + let _spi_nss = gpioe + .pe4 + .into_alternate_af5() + .set_speed(hal::gpio::Speed::VeryHigh); + + let config = hal::spi::Config::new(hal::spi::Mode { + polarity: hal::spi::Polarity::IdleHigh, + phase: hal::spi::Phase::CaptureOnSecondTransition, + }) + .manage_cs() + .suspend_when_inactive() + .communication_mode(hal::spi::CommunicationMode::Transmitter) + .swap_mosi_miso(); + + dp.SPI4.spi( + (spi_sck, spi_miso, hal::spi::NoMosi), + config, + 50.mhz(), + ccdr.peripheral.SPI4, + &ccdr.clocks, + ) + }; + + let dac1_spi = { + let spi_miso = gpiof + .pf8 + .into_alternate_af5() + .set_speed(hal::gpio::Speed::VeryHigh); + let spi_sck = gpiof + .pf7 + .into_alternate_af5() + .set_speed(hal::gpio::Speed::VeryHigh); + let _spi_nss = gpiof + .pf6 + .into_alternate_af5() + .set_speed(hal::gpio::Speed::VeryHigh); + + let config = hal::spi::Config::new(hal::spi::Mode { + polarity: hal::spi::Polarity::IdleHigh, + phase: hal::spi::Phase::CaptureOnSecondTransition, + }) + .manage_cs() + .communication_mode(hal::spi::CommunicationMode::Transmitter) + .suspend_when_inactive() + .swap_mosi_miso(); + + dp.SPI5.spi( + (spi_sck, spi_miso, hal::spi::NoMosi), + config, + 50.mhz(), + ccdr.peripheral.SPI5, + &ccdr.clocks, + ) + }; + + let timer = dp.TIM3.timer( + SAMPLE_FREQUENCY_KHZ.khz(), + ccdr.peripheral.TIM3, + &ccdr.clocks, ); - spi.listen(hal::spi::Event::Eot); - - spi - }; - - let adc1_spi = { - let spi_miso = gpiob - .pb4 - .into_alternate_af6() - .set_speed(hal::gpio::Speed::VeryHigh); - let spi_sck = gpioc - .pc10 - .into_alternate_af6() - .set_speed(hal::gpio::Speed::VeryHigh); - let _spi_nss = gpioa - .pa15 - .into_alternate_af6() - .set_speed(hal::gpio::Speed::VeryHigh); - - let config = hal::spi::Config::new(hal::spi::Mode { - polarity: hal::spi::Polarity::IdleHigh, - phase: hal::spi::Phase::CaptureOnSecondTransition, - }) - .communication_mode(hal::spi::CommunicationMode::Receiver) - .manage_cs() - .transfer_size(1) - .frame_size(16) - .cs_delay(220e-9); - - let mut spi = dp.SPI3.spi( - (spi_sck, spi_miso, hal::spi::NoMosi), - config, - 50.mhz(), - &clocks, - ); - - spi.listen(hal::spi::Event::Eot); - - spi - }; - - let _dac_clr_n = gpioe.pe12.into_push_pull_output().set_high().unwrap(); - let _dac0_ldac_n = - gpioe.pe11.into_push_pull_output().set_low().unwrap(); - let _dac1_ldac_n = - gpioe.pe15.into_push_pull_output().set_low().unwrap(); - - let dac0_spi = { - let spi_miso = gpioe - .pe5 - .into_alternate_af5() - .set_speed(hal::gpio::Speed::VeryHigh); - let spi_sck = gpioe - .pe2 - .into_alternate_af5() - .set_speed(hal::gpio::Speed::VeryHigh); - let _spi_nss = gpioe - .pe4 - .into_alternate_af5() - .set_speed(hal::gpio::Speed::VeryHigh); - - let config = hal::spi::Config::new(hal::spi::Mode { - polarity: hal::spi::Polarity::IdleHigh, - phase: hal::spi::Phase::CaptureOnSecondTransition, - }) - .communication_mode(hal::spi::CommunicationMode::Transmitter) - .manage_cs() - .transfer_size(1) - .frame_size(16) - .swap_mosi_miso(); - - dp.SPI4.spi( - (spi_sck, spi_miso, hal::spi::NoMosi), - config, - 50.mhz(), - &clocks, - ) - }; - - let dac1_spi = { - let spi_miso = gpiof - .pf8 - .into_alternate_af5() - .set_speed(hal::gpio::Speed::VeryHigh); - let spi_sck = gpiof - .pf7 - .into_alternate_af5() - .set_speed(hal::gpio::Speed::VeryHigh); - let _spi_nss = gpiof - .pf6 - .into_alternate_af5() - .set_speed(hal::gpio::Speed::VeryHigh); - - let config = hal::spi::Config::new(hal::spi::Mode { - polarity: hal::spi::Polarity::IdleHigh, - phase: hal::spi::Phase::CaptureOnSecondTransition, - }) - .communication_mode(hal::spi::CommunicationMode::Transmitter) - .manage_cs() - .transfer_size(1) - .frame_size(16) - .swap_mosi_miso(); - - dp.SPI5.spi( - (spi_sck, spi_miso, hal::spi::NoMosi), - config, - 50.mhz(), - &clocks, - ) + DacOutputs::new(dac0_spi, dac1_spi, timer) }; let mut fp_led_0 = gpiod.pd5.into_push_pull_output(); @@ -413,36 +427,44 @@ const APP: () = { let ad9959 = { let qspi_interface = { // Instantiate the QUADSPI pins and peripheral interface. - // TODO: Place these into a pins structure that is provided to the QSPI - // constructor. - let _qspi_clk = gpiob - .pb2 - .into_alternate_af9() - .set_speed(hal::gpio::Speed::VeryHigh); - let _qspi_ncs = gpioc - .pc11 - .into_alternate_af9() - .set_speed(hal::gpio::Speed::VeryHigh); - let _qspi_io0 = gpioe - .pe7 - .into_alternate_af10() - .set_speed(hal::gpio::Speed::VeryHigh); - let _qspi_io1 = gpioe - .pe8 - .into_alternate_af10() - .set_speed(hal::gpio::Speed::VeryHigh); - let _qspi_io2 = gpioe - .pe9 - .into_alternate_af10() - .set_speed(hal::gpio::Speed::VeryHigh); - let _qspi_io3 = gpioe - .pe10 - .into_alternate_af10() - .set_speed(hal::gpio::Speed::VeryHigh); + let qspi_pins = { + let _qspi_ncs = gpioc + .pc11 + .into_alternate_af9() + .set_speed(hal::gpio::Speed::VeryHigh); + + let clk = gpiob + .pb2 + .into_alternate_af9() + .set_speed(hal::gpio::Speed::VeryHigh); + let io0 = gpioe + .pe7 + .into_alternate_af10() + .set_speed(hal::gpio::Speed::VeryHigh); + let io1 = gpioe + .pe8 + .into_alternate_af10() + .set_speed(hal::gpio::Speed::VeryHigh); + let io2 = gpioe + .pe9 + .into_alternate_af10() + .set_speed(hal::gpio::Speed::VeryHigh); + let io3 = gpioe + .pe10 + .into_alternate_af10() + .set_speed(hal::gpio::Speed::VeryHigh); + + (clk, io0, io1, io2, io3) + }; + + let qspi = hal::qspi::Qspi::bank2( + dp.QUADSPI, + qspi_pins, + 50.mhz(), + &ccdr.clocks, + ccdr.peripheral.QSPI, + ); - let qspi = - hal::qspi::Qspi::new(dp.QUADSPI, &mut clocks, 50.mhz()) - .unwrap(); pounder::QspiInterface::new(qspi).unwrap() }; @@ -462,7 +484,12 @@ const APP: () = { let io_expander = { let sda = gpiob.pb7.into_alternate_af4().set_open_drain(); let scl = gpiob.pb8.into_alternate_af4().set_open_drain(); - let i2c1 = dp.I2C1.i2c((scl, sda), 100.khz(), &clocks); + let i2c1 = dp.I2C1.i2c( + (scl, sda), + 100.khz(), + ccdr.peripheral.I2C1, + &ccdr.clocks, + ); mcp23017::MCP23017::default(i2c1).unwrap() }; @@ -483,8 +510,7 @@ const APP: () = { let config = hal::spi::Config::new(hal::spi::Mode { polarity: hal::spi::Polarity::IdleHigh, phase: hal::spi::Phase::CaptureOnSecondTransition, - }) - .frame_size(8); + }); // The maximum frequency of this SPI must be limited due to capacitance on the MISO // line causing a long RC decay. @@ -492,22 +518,31 @@ const APP: () = { (spi_sck, spi_miso, spi_mosi), config, 5.mhz(), - &clocks, + ccdr.peripheral.SPI1, + &ccdr.clocks, ) }; - let adc1 = { - let mut adc = dp.ADC1.adc(&mut delay, &mut clocks); - adc.calibrate(); + let (adc1, adc2) = { + let (mut adc1, mut adc2) = hal::adc::adc12( + dp.ADC1, + dp.ADC2, + &mut delay, + ccdr.peripheral.ADC12, + &ccdr.clocks, + ); - adc.enable() - }; + let adc1 = { + adc1.calibrate(); + adc1.enable() + }; - let adc2 = { - let mut adc = dp.ADC2.adc(&mut delay, &mut clocks); - adc.calibrate(); + let adc2 = { + adc2.calibrate(); + adc2.enable() + }; - adc.enable() + (adc1, adc2) }; let adc1_in_p = gpiof.pf11.into_analog(); @@ -561,7 +596,12 @@ const APP: () = { let mut eeprom_i2c = { let sda = gpiof.pf0.into_alternate_af4().set_open_drain(); let scl = gpiof.pf1.into_alternate_af4().set_open_drain(); - dp.I2C2.i2c((scl, sda), 100.khz(), &clocks) + dp.I2C2.i2c( + (scl, sda), + 100.khz(), + ccdr.peripheral.I2C2, + &ccdr.clocks, + ) }; // Configure ethernet pins. @@ -620,15 +660,23 @@ const APP: () = { let (network_interface, eth_mac) = { // Configure the ethernet controller let (eth_dma, eth_mac) = unsafe { - ethernet::ethernet_init( + ethernet::new_unchecked( dp.ETHERNET_MAC, dp.ETHERNET_MTL, dp.ETHERNET_DMA, &mut DES_RING, mac_addr.clone(), + ccdr.peripheral.ETH1MAC, + &ccdr.clocks, ) }; + // Reset and initialize the ethernet phy. + let mut lan8742a = + ethernet::phy::LAN8742A::new(eth_mac.set_phy_addr(0)); + lan8742a.phy_reset(); + lan8742a.phy_init(); + unsafe { ethernet::enable_interrupt() }; let store = unsafe { &mut NET_STORE }; @@ -647,7 +695,7 @@ const APP: () = { .ip_addrs(&mut store.ip_addrs[..]) .finalize(); - (interface, eth_mac) + (interface, lan8742a) }; cp.SCB.enable_icache(); @@ -660,37 +708,23 @@ const APP: () = { // Utilize the cycle counter for RTIC scheduling. cp.DWT.enable_cycle_counter(); - let mut dma = hal::dma::Dma::dma(dp.DMA1, dp.DMAMUX1, &clocks); - dma.configure_m2p_stream( - hal::dma::Stream::One, - &SPI_START_CODE as *const _ as u32, - &adc0_spi.spi.cr1 as *const _ as u32, - hal::dma::DMAREQ_ID::TIM2_CH1, - ); - - dma.configure_m2p_stream( - hal::dma::Stream::Two, - &SPI_START_CODE as *const _ as u32, - &adc1_spi.spi.cr1 as *const _ as u32, - hal::dma::DMAREQ_ID::TIM2_CH2, - ); - // Configure timer 2 to trigger conversions for the ADC - let mut timer2 = dp.TIM2.timer(50.khz(), &mut clocks); - timer2.configure_channel(hal::timer::Channel::One, 0.25); - timer2.configure_channel(hal::timer::Channel::Two, 0.75); - - timer2.listen(hal::timer::Event::ChannelOneDma); - timer2.listen(hal::timer::Event::ChannelTwoDma); + let timer2 = dp.TIM2.timer( + SAMPLE_FREQUENCY_KHZ.khz(), + ccdr.peripheral.TIM2, + &ccdr.clocks, + ); + { + let t2_regs = unsafe { &*hal::stm32::TIM2::ptr() }; + t2_regs.dier.modify(|_, w| w.ude().set_bit()); + } init::LateResources { afe0: afe0, - adc0: adc0_spi, - dac0: dac0_spi, - afe1: afe1, - adc1: adc1_spi, - dac1: dac1_spi, + + adcs, + dacs, timer: timer2, pounder: pounder_devices, @@ -702,44 +736,27 @@ const APP: () = { } } - #[task(binds = SPI3, resources = [adc1, dac1, iir_state, iir_ch], priority = 2)] - fn spi3(c: spi3::Context) { - c.resources.adc1.spi.ifcr.write(|w| w.eotc().set_bit()); - - let output: u16 = { - let a: u16 = c.resources.adc1.read().unwrap(); - let x0 = f32::from(a as i16); - let y0 = - c.resources.iir_ch[1].update(&mut c.resources.iir_state[1], x0); - y0 as i16 as u16 ^ 0x8000 - }; - - c.resources - .dac1 - .spi - .ifcr - .write(|w| w.eotc().set_bit().txtfc().set_bit()); - c.resources.dac1.send(output).unwrap(); + #[task(binds = TIM3, resources=[dacs], priority = 3)] + fn dac_update(c: dac_update::Context) { + c.resources.dacs.update(); } - #[task(binds = SPI2, resources = [adc0, dac0, iir_state, iir_ch], priority = 2)] - fn spi2(c: spi2::Context) { - c.resources.adc0.spi.ifcr.write(|w| w.eotc().set_bit()); + #[task(binds=DMA1_STR3, resources=[adcs, dacs, iir_state, iir_ch], priority=2)] + fn adc_update(mut c: adc_update::Context) { + let (adc0_samples, adc1_samples) = + c.resources.adcs.transfer_complete_handler(); - let output: u16 = { - let a: u16 = c.resources.adc0.read().unwrap(); - let x0 = f32::from(a as i16); - let y0 = - c.resources.iir_ch[0].update(&mut c.resources.iir_state[0], x0); - y0 as i16 as u16 ^ 0x8000 - }; + for (adc0, adc1) in adc0_samples.iter().zip(adc1_samples.iter()) { + let result_adc0 = c.resources.iir_ch[0] + .update_from_adc_sample(*adc0, &mut c.resources.iir_state[0]); - c.resources - .dac0 - .spi - .ifcr - .write(|w| w.eotc().set_bit().txtfc().set_bit()); - c.resources.dac0.send(output).unwrap(); + let result_adc1 = c.resources.iir_ch[1] + .update_from_adc_sample(*adc1, &mut c.resources.iir_state[1]); + + c.resources + .dacs + .lock(|dacs| dacs.push(result_adc0, result_adc1)); + } } #[idle(resources=[net_interface, pounder, mac_addr, eth_mac, iir_state, iir_ch, afe0, afe1])] @@ -904,6 +921,16 @@ const APP: () = { unsafe { ethernet::interrupt_handler() } } + #[task(binds = SPI2, priority = 1)] + fn spi2(_: spi2::Context) { + panic!("ADC0 input overrun"); + } + + #[task(binds = SPI3, priority = 1)] + fn spi3(_: spi3::Context) { + panic!("ADC0 input overrun"); + } + extern "C" { // hw interrupt handlers for RTIC to use for scheduling tasks // one per priority diff --git a/src/pounder/mod.rs b/src/pounder/mod.rs index 1e3c8c9..6b637f4 100644 --- a/src/pounder/mod.rs +++ b/src/pounder/mod.rs @@ -290,7 +290,7 @@ pub struct PounderDevices { pub ad9959: ad9959::Ad9959, pub io_update_trigger: HighResTimerE, mcp23017: mcp23017::MCP23017>, - attenuator_spi: hal::spi::Spi, + attenuator_spi: hal::spi::Spi, adc1: hal::adc::Adc, adc2: hal::adc::Adc, adc1_in_p: hal::gpio::gpiof::PF11, @@ -312,7 +312,7 @@ impl PounderDevices { mcp23017: mcp23017::MCP23017>, ad9959: ad9959::Ad9959, io_update_trigger: HighResTimerE, - attenuator_spi: hal::spi::Spi, + attenuator_spi: hal::spi::Spi, adc1: hal::adc::Adc, adc2: hal::adc::Adc, adc1_in_p: hal::gpio::gpiof::PF11,