From 754ebed50db05d05859bc2b6076c527bbfbb0e06 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Robert=20J=C3=B6rdens?= <rj@quartiq.de>
Date: Thu, 26 Nov 2020 11:55:15 +0100
Subject: [PATCH] adc: transfer complete interrupt on Adc1

---
 src/adc.rs | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/adc.rs b/src/adc.rs
index a16976a..2849f00 100644
--- a/src/adc.rs
+++ b/src/adc.rs
@@ -137,6 +137,7 @@ macro_rules! adc_input {
                 // data stream is used to trigger a transfer completion interrupt.
                 let data_config = DmaConfig::default()
                     .memory_increment(true)
+                    .transfer_complete_interrupt($index == 1)
                     .priority(Priority::VeryHigh);
 
                 // A SPI peripheral error interrupt is used to determine if the RX FIFO overflows. This