adc: transfer complete interrupt on Adc1

2020-11-26 11:55:15 +01:00 · 2020-11-26 11:55:15 +01:00 · 754ebed50d
commit 754ebed50d
parent 7189830896
1 changed files with 1 additions and 0 deletions
--- a/src/adc.rs
+++ b/src/adc.rs
@ -137,6 +137,7 @@ macro_rules! adc_input {
                // data stream is used to trigger a transfer completion interrupt.
                let data_config = DmaConfig::default()
                    .memory_increment(true)
+                    .transfer_complete_interrupt($index == 1)
                    .priority(Priority::VeryHigh);

                // A SPI peripheral error interrupt is used to determine if the RX FIFO overflows. This