cleanup iir
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dc2e0f8b07
commit
74f10a7ac4
45
src/iir.rs
45
src/iir.rs
@ -10,34 +10,37 @@ pub struct IIR {
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pub scale: f32,
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pub scale: f32,
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}
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}
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fn abs(x: f32) -> f32 {
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if x >= 0. { x } else { -x }
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}
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fn copysign(x: f32, y: f32) -> f32 {
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match () {
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_ if (x >= 0. && y >= 0.) || (x <= 0. && y <= 0.) => y,
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_ => -y
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}
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}
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impl IIR {
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impl IIR {
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pub fn pi(&mut self, kp: f32, ki: f32, g: f32) -> Result<(), &str> {
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pub fn pi(&mut self, kp: f32, ki: f32, g: f32) -> Result<(), &str> {
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if ki < 0. {
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let ki = copysign(kp, ki);
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return Err("ki < 0");
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let g = copysign(kp, g);
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}
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let (a1, b0, b1) = match () {
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let (a1, b1, b0) = match () {
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_ if abs(ki) < f32::EPSILON => (0., kp, 0.),
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_ if ki < 0. => return Err("ki < 0"),
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_ if ki < f32::EPSILON => (0., 0., kp),
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_ => {
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_ => {
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let (c, a1) = match () {
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let c = match () {
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_ if g < 0. => return Err("g < 0"),
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_ if abs(g) < f32::EPSILON => 1.,
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_ if g < f32::EPSILON => (1., 1.),
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_ => 1./(1. + ki/g)
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_ => {
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let c = 1./(1. + ki/g);
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(c, 2.*c - 1.)
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}
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};
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};
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let b0 = kp + ki*c;
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let a1 = 2.*c - 1.;
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let b1 = b0 - 2.*kp*c;
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let b0 = ki*c + kp;
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if b0 + b1 > -f32::EPSILON && b0 + b1 < f32::EPSILON {
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let b1 = ki*c - a1*kp;
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return Err("low integrator gain and/or gain limit");
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if abs(b0 + b1) < f32::EPSILON {
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return Err("low integrator gain and/or gain limit")
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}
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}
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(a1, b1, b0)
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(a1, b0, b1)
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}
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}
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};
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};
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if b0 > 1. || b0 < -1. || b1 > 1. || b1 < -1. {
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return Err("high gains");
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}
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self.ba[0] = b0;
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self.ba[0] = b0;
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self.ba[1] = b1;
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self.ba[1] = b1;
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self.ba[2] = 0.;
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self.ba[2] = 0.;
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@ -542,8 +542,8 @@ fn main() -> ! {
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rcc.apb1lenr.modify(|_, w| w.tim2en().set_bit());
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rcc.apb1lenr.modify(|_, w| w.tim2en().set_bit());
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tim2_setup(&dp.TIM2);
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tim2_setup(&dp.TIM2);
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unsafe { IIR_CH[0].pi(-0.1, 10.*2e-6/2., 0.).expect("bad coefficients"); }
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unsafe { IIR_CH[0].pi(0.1, 10.*2e-6/2., 0.).expect("bad coefficients"); }
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unsafe { IIR_CH[1].pi(0.1, 10.*2e-6/2., 0.).expect("bad coefficients"); }
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unsafe { IIR_CH[1].pi(-0.1, 10.*2e-6/2., 0.).expect("bad coefficients"); }
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cortex_m::interrupt::free(|cs| {
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cortex_m::interrupt::free(|cs| {
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cp.NVIC.enable(stm32::Interrupt::SPI1);
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cp.NVIC.enable(stm32::Interrupt::SPI1);
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