rcc: pac 0.9 renames
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@ -149,9 +149,9 @@ fn rcc_pll_setup(rcc: &pac::RCC, flash: &pac::FLASH) {
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// Configure PLL2: 8MHz /1 *25 / 2 = 100 MHz
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// Configure PLL2: 8MHz /1 *25 / 2 = 100 MHz
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rcc.pll2divr.write(|w| unsafe {
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rcc.pll2divr.write(|w| unsafe {
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w.divn1().bits(25 - 1) // feebdack divider
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w.divn2().bits(25 - 1) // feebdack divider
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.divp1().bits(2 - 1) // p output divider
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.divp2().bits(2 - 1) // p output divider
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.divq1().bits(2 - 1) // q output divider
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.divq2().bits(2 - 1) // q output divider
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});
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});
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rcc.cr.modify(|_, w| w.pll2on().on());
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rcc.cr.modify(|_, w| w.pll2on().on());
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while !rcc.cr.read().pll2rdy().is_ready() {}
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while !rcc.cr.read().pll2rdy().is_ready() {}
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