From 56366a013fe647735e957ffcb80f9ad109679483 Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Wed, 6 Jan 2021 15:34:12 +0100 Subject: [PATCH] Specifying consequences of failing to meet timing --- src/dac.rs | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/dac.rs b/src/dac.rs index efa9588..109dc78 100644 --- a/src/dac.rs +++ b/src/dac.rs @@ -21,7 +21,8 @@ ///! transfer completion is handled). In this mode, by the time DMA swaps buffers, there is always a valid buffer in the ///! "next-transfer" double-buffer location for the DMA transfer. Once a transfer completes, ///! software then has exactly one batch duration to fill the next buffer before its -///! transfer begins. +///! transfer begins. If software does not meet this deadline, old data will be repeatedly generated +///! on the output and output will be shifted by one batch. ///! ///! ## Multiple Samples to Single DAC Codes ///!