diff --git a/Cargo.lock b/Cargo.lock index 915290b..ff768f0 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -567,6 +567,7 @@ dependencies = [ [[package]] name = "stm32h7xx-hal" version = "0.8.0" +source = "git+https://github.com/quartiq/stm32h7xx-hal?branch=feature/stabilizer-dma#5fbbfa9352f720994c210e5c21601f3acf9dc40c" dependencies = [ "bare-metal 1.0.0", "cast", diff --git a/src/adc.rs b/src/adc.rs index 15d2f63..dd006f1 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -1,5 +1,7 @@ -use super::{hal, DmaConfig, PeripheralToMemory, MemoryToPeripheral, TargetAddress, Transfer, DMAReq, -Stream}; +use super::{ + hal, DMAReq, DmaConfig, MemoryToPeripheral, PeripheralToMemory, Stream, + TargetAddress, Transfer, +}; const INPUT_BUFFER_SIZE: usize = 1; @@ -62,7 +64,8 @@ pub struct Adc0Input { hal::dma::dma::Stream1, hal::spi::Spi, PeripheralToMemory, - &'static mut [u16; INPUT_BUFFER_SIZE]>, + &'static mut [u16; INPUT_BUFFER_SIZE], + >, } impl Adc0Input { @@ -76,12 +79,14 @@ impl Adc0Input { .peripheral_increment(false) .circular_buffer(true); - let mut trigger_transfer: Transfer<_, _, MemoryToPeripheral, _ > = Transfer::init( - trigger_stream, - &SPI2::new(), - unsafe { &mut SPI_START }, - None, - trigger_config); + let mut trigger_transfer: Transfer<_, _, MemoryToPeripheral, _> = + Transfer::init( + trigger_stream, + &SPI2::new(), + unsafe { &mut SPI_START }, + None, + trigger_config, + ); let data_config = DmaConfig::default() .memory_increment(true) @@ -91,12 +96,14 @@ impl Adc0Input { let mut spi = spi.disable(); spi.listen(hal::spi::Event::Error); - let mut data_transfer: Transfer<_, _, PeripheralToMemory, _ > = Transfer::init( - data_stream, - &spi, - unsafe { &mut ADC0_BUF0 }, - None, - data_config); + let mut data_transfer: Transfer<_, _, PeripheralToMemory, _> = + Transfer::init( + data_stream, + &spi, + unsafe { &mut ADC0_BUF0 }, + None, + data_config, + ); spi.enable_dma_rx(); spi.enable_dma_tx(); @@ -115,7 +122,8 @@ impl Adc0Input { pub fn transfer_complete_handler(&mut self) -> &[u16; INPUT_BUFFER_SIZE] { let next_buffer = self.next_buffer.take().unwrap(); - let (prev_buffer, _) = self.transfer.next_transfer(next_buffer).unwrap(); + let (prev_buffer, _) = + self.transfer.next_transfer(next_buffer).unwrap(); self.next_buffer.replace(prev_buffer); self.next_buffer.as_ref().unwrap() } @@ -127,7 +135,8 @@ pub struct Adc1Input { hal::dma::dma::Stream3, hal::spi::Spi, PeripheralToMemory, - &'static mut [u16; INPUT_BUFFER_SIZE]>, + &'static mut [u16; INPUT_BUFFER_SIZE], + >, } impl Adc1Input { @@ -141,12 +150,14 @@ impl Adc1Input { .peripheral_increment(false) .circular_buffer(true); - let mut trigger_transfer: Transfer<_, _, MemoryToPeripheral, _ > = Transfer::init( - trigger_stream, - &SPI3::new(), - unsafe { &mut SPI_START }, - None, - trigger_config); + let mut trigger_transfer: Transfer<_, _, MemoryToPeripheral, _> = + Transfer::init( + trigger_stream, + &SPI3::new(), + unsafe { &mut SPI_START }, + None, + trigger_config, + ); let data_config = DmaConfig::default() .memory_increment(true) @@ -156,12 +167,14 @@ impl Adc1Input { let mut spi = spi.disable(); spi.listen(hal::spi::Event::Error); - let mut data_transfer: Transfer<_, _, PeripheralToMemory, _ > = Transfer::init( - data_stream, - &spi, - unsafe { &mut ADC1_BUF0 }, - None, - data_config); + let mut data_transfer: Transfer<_, _, PeripheralToMemory, _> = + Transfer::init( + data_stream, + &spi, + unsafe { &mut ADC1_BUF0 }, + None, + data_config, + ); spi.enable_dma_rx(); spi.enable_dma_tx(); @@ -180,7 +193,8 @@ impl Adc1Input { pub fn transfer_complete_handler(&mut self) -> &[u16; INPUT_BUFFER_SIZE] { let next_buffer = self.next_buffer.take().unwrap(); - let (prev_buffer, _) = self.transfer.next_transfer(next_buffer).unwrap(); + let (prev_buffer, _) = + self.transfer.next_transfer(next_buffer).unwrap(); self.next_buffer.replace(prev_buffer); self.next_buffer.as_ref().unwrap() } diff --git a/src/dac.rs b/src/dac.rs index fb5f4ab..575320d 100644 --- a/src/dac.rs +++ b/src/dac.rs @@ -1,4 +1,3 @@ - use super::hal; use heapless::consts; @@ -8,9 +7,14 @@ pub struct Dac0Output { } impl Dac0Output { - pub fn new(spi: hal::spi::Spi) -> Self { + pub fn new( + spi: hal::spi::Spi, + ) -> Self { spi.inner().cr1.modify(|_, w| w.cstart().started()); - Self { spi, outputs: heapless::spsc::Queue::new() } + Self { + spi, + outputs: heapless::spsc::Queue::new(), + } } pub fn push(&mut self, value: u16) { @@ -20,13 +24,16 @@ impl Dac0Output { pub fn update(&mut self) { match self.outputs.dequeue() { Some(value) => self.write(value), - None => {}, + None => {} } } pub fn write(&mut self, value: u16) { unsafe { - core::ptr::write_volatile(&self.spi.inner().txdr as *const _ as *mut u16, value); + core::ptr::write_volatile( + &self.spi.inner().txdr as *const _ as *mut u16, + value, + ); } } } @@ -42,7 +49,10 @@ impl Dac1Output { ) -> Self { spi.inner().cr1.modify(|_, w| w.cstart().started()); - Self { spi, outputs: heapless::spsc::Queue::new() } + Self { + spi, + outputs: heapless::spsc::Queue::new(), + } } pub fn push(&mut self, value: u16) { @@ -52,13 +62,16 @@ impl Dac1Output { pub fn update(&mut self) { match self.outputs.dequeue() { Some(value) => self.write(value), - None => {}, + None => {} } } pub fn write(&mut self, value: u16) { unsafe { - core::ptr::write_volatile(&self.spi.inner().txdr as *const _ as *mut u16, value); + core::ptr::write_volatile( + &self.spi.inner().txdr as *const _ as *mut u16, + value, + ); } } } diff --git a/src/main.rs b/src/main.rs index 91058ba..72d0db2 100644 --- a/src/main.rs +++ b/src/main.rs @@ -36,13 +36,9 @@ use embedded_hal::digital::v2::{InputPin, OutputPin}; use hal::{ dma::{ - Transfer, - PeripheralToMemory, MemoryToPeripheral, + dma::{DMAReq, DmaConfig}, traits::{Stream, TargetAddress}, - dma::{ - DmaConfig, - DMAReq, - }, + MemoryToPeripheral, PeripheralToMemory, Transfer, }, ethernet::{self, PHY}, }; @@ -53,16 +49,16 @@ use heapless::{consts::*, String}; #[link_section = ".sram3.eth"] static mut DES_RING: ethernet::DesRing = ethernet::DesRing::new(); -mod dac; mod adc; mod afe; +mod dac; mod eeprom; mod iir; mod pounder; mod server; -use dac::{Dac0Output, Dac1Output}; use adc::{Adc0Input, Adc1Input}; +use dac::{Dac0Output, Dac1Output}; #[cfg(not(feature = "semihosting"))] fn init_log() {} @@ -257,7 +253,8 @@ const APP: () = { afe::ProgrammableGainAmplifier::new(a0_pin, a1_pin) }; - let dma_streams = hal::dma::dma::StreamsTuple::new(dp.DMA1, ccdr.peripheral.DMA1); + let dma_streams = + hal::dma::dma::StreamsTuple::new(dp.DMA1, ccdr.peripheral.DMA1); // Configure the SPI interfaces to the ADCs and DACs. let adc0 = { @@ -714,7 +711,8 @@ const APP: () = { let mut last_result: u16 = 0; for sample in samples { let x0 = f32::from(*sample as i16); - let y0 = c.resources.iir_ch[1].update(&mut c.resources.iir_state[1], x0); + let y0 = + c.resources.iir_ch[1].update(&mut c.resources.iir_state[1], x0); last_result = y0 as i16 as u16 ^ 0x8000; //c.resources.dac0.push(last_result); } @@ -729,7 +727,8 @@ const APP: () = { let mut last_result: u16 = 0; for sample in samples { let x0 = f32::from(*sample as i16); - let y0 = c.resources.iir_ch[0].update(&mut c.resources.iir_state[0], x0); + let y0 = + c.resources.iir_ch[0].update(&mut c.resources.iir_state[0], x0); last_result = y0 as i16 as u16 ^ 0x8000; //c.resources.dac0.push(last_result); }