itcm: implement in rust and execute during setup()
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2
.github/workflows/ci.yml
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2
.github/workflows/ci.yml
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@ -16,7 +16,6 @@ jobs:
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runs-on: ubuntu-latest
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steps:
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- uses: actions/checkout@v2
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- run: sudo apt install gcc-arm-none-eabi
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- uses: actions-rs/toolchain@v1
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with:
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toolchain: stable
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@ -52,7 +51,6 @@ jobs:
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features: nightly
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steps:
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- uses: actions/checkout@v2
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- run: sudo apt install gcc-arm-none-eabi
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- uses: actions-rs/toolchain@v1
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with:
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toolchain: ${{ matrix.toolchain }}
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1
.github/workflows/release.yml
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1
.github/workflows/release.yml
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@ -12,7 +12,6 @@ jobs:
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runs-on: ubuntu-latest
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steps:
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- uses: actions/checkout@v2
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- run: sudo apt install gcc-arm-none-eabi
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- uses: actions-rs/toolchain@v1
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with:
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toolchain: stable
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7
Cargo.lock
generated
7
Cargo.lock
generated
@ -102,12 +102,6 @@ dependencies = [
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"rustc_version",
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]
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[[package]]
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name = "cc"
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version = "1.0.67"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "e3c69b077ad434294d3ce9f1f6143a2a4b89a8a2d54ef813d85003a4fd1137fd"
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[[package]]
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name = "cfg-if"
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version = "1.0.0"
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@ -756,7 +750,6 @@ version = "0.5.0"
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dependencies = [
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"ad9959",
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"asm-delay",
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"cc",
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"cortex-m 0.7.2",
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"cortex-m-rt",
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"cortex-m-rtic",
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@ -58,9 +58,6 @@ rev = "61933f857a"
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features = ["stm32h743v", "rt", "unproven", "ethernet", "quadspi"]
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version = "0.9.0"
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[build-dependencies]
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cc = "1.0"
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[patch.crates-io.cortex-m-rt]
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git = "https://github.com/rust-embedded/cortex-m-rt.git"
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rev = "a2e3ad5"
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3
build.rs
3
build.rs
@ -1,6 +1,3 @@
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fn main() {
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println!("cargo:rerun-if-changed=memory.x");
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cc::Build::new().file("src/startup.S").compile("startup");
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println!("cargo:rerun-if-changed=src/startup.S");
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}
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@ -105,6 +105,32 @@ pub struct PounderDevices {
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/// Static storage for the ethernet DMA descriptor ring.
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static mut DES_RING: ethernet::DesRing = ethernet::DesRing::new();
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/// Setup ITCM and load its code from flash
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unsafe fn setup_itcm() {
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extern "C" {
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static mut __sitcm: u32;
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static mut __eitcm: u32;
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static mut __siitcm: u32;
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}
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use core::{ptr, slice, sync::atomic};
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// ITCM is enabled on reset on our CPU but might not be on others.
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// Keep for completeness.
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const ITCMCR: *mut u32 = 0xE000_EF90usize as _;
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ptr::write_volatile(ITCMCR, ptr::read_volatile(ITCMCR) | 1);
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atomic::fence(atomic::Ordering::SeqCst);
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let len =
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(&__eitcm as *const u32).offset_from(&__sitcm as *const _) as usize;
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let dst = slice::from_raw_parts_mut(&mut __sitcm as *mut _, len);
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let src = slice::from_raw_parts(&__siitcm as *const _, len);
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dst.copy_from_slice(src);
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atomic::fence(atomic::Ordering::SeqCst);
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cortex_m::asm::dsb();
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cortex_m::asm::isb();
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}
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/// Configure the stabilizer hardware for operation.
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///
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/// # Args
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@ -160,6 +186,10 @@ pub fn setup(
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log::info!("starting...");
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}
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unsafe {
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setup_itcm();
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}
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// Set up the system timer for RTIC scheduling.
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{
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let tim15 =
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@ -1,44 +0,0 @@
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.cfi_sections .debug_frame
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# .thumb
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.section .text.pre_init, "ax"
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.globl __pre_init
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.type __pre_init,%function
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.thumb_func
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.cfi_startproc
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__pre_init:
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# Enable ITCM and DTCM
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ldr r0, =1
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ldr r1, =0xE000EF90
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ldr r2, [r1]
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# Set ITCMCR.EN
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orr r2, r2, r0
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str r2, [r1]
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ldr r1, =0xE000EF94
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ldr r2, [r1]
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# Set DTCMCR.EN
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orr r2, r2, r0
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str r2, [r1]
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dsb
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isb
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# Analogous to cortex-m-rt Reset code for .data copying.
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# Initialise .itcm code. `__sitcm`, `__siitcm`, and `__eitcm` come from the
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# linker script. Copy from r2 into r0 until r0 reaches r1.
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ldr r0,=__sitcm
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ldr r1,=__eitcm
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ldr r2,=__siitcm
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1:
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cmp r1, r0
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beq 2f
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# load 1 word from r2 to r3, inc r2
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ldm r2!, {r3}
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# store 1 word from r3 to r0, inc r0
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stm r0!, {r3}
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b 1b
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2:
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dsb
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isb
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bx lr
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.cfi_endproc
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