From 44c36b203d9e56c3da5da2f7a49dfbcb6228a19e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Robert=20J=C3=B6rdens?= <rj@quartiq.de>
Date: Mon, 18 Mar 2019 13:10:00 +0000
Subject: [PATCH] working

---
 memory.x       |  10 ++++-
 stabilizer.cfg |  10 ++---
 stm32h7.cfg    | 112 -------------------------------------------------
 3 files changed, 11 insertions(+), 121 deletions(-)
 delete mode 100644 stm32h7.cfg

diff --git a/memory.x b/memory.x
index 2d59134..7793179 100644
--- a/memory.x
+++ b/memory.x
@@ -1,5 +1,11 @@
 MEMORY
 {
-  FLASH : ORIGIN = 0x08000000, LENGTH = 512K
-  RAM : ORIGIN = 0x20000000, LENGTH = 112K  /* of 112K + 16K */
+  ITCM   : ORIGIN = 0x00000000, LENGTH = 64K
+  RAM    : ORIGIN = 0x20000000, LENGTH = 128K
+  RAM_D1 : ORIGIN = 0x24000000, LENGTH = 512K
+  RAM_D2 : ORIGIN = 0x30000000, LENGTH = 288K
+  RAM_D3 : ORIGIN = 0x38000000, LENGTH = 64K
+  RAM_B  : ORIGIN = 0x38800000, LENGTH = 4K
+  FLASH  : ORIGIN = 0x08000000, LENGTH = 1024K
+  FLASH1 : ORIGIN = 0x08100000, LENGTH = 1024K
 }
diff --git a/stabilizer.cfg b/stabilizer.cfg
index 1ab4c0c..51d7c6c 100644
--- a/stabilizer.cfg
+++ b/stabilizer.cfg
@@ -1,10 +1,6 @@
 source [find interface/stlink.cfg]
 transport select hla_swd
+source [find target/stm32h7x_dual_bank.cfg]
 
-source [find stm32h7x.cfg]
-# STM32H7xxxI 2Mo have a dual bank flash.
-# Add the second flash bank.
-set _FLASHNAME $_CHIPNAME.flash1
-flash bank $_FLASHNAME stm32h7x 0x08100000 0 0 0 $_TARGETNAME
-
-reset_config srst_only
+# reset_config srst_only
+reset_config none
diff --git a/stm32h7.cfg b/stm32h7.cfg
deleted file mode 100644
index 735b392..0000000
--- a/stm32h7.cfg
+++ /dev/null
@@ -1,112 +0,0 @@
-# script for stm32h7x family
-
-#
-# stm32h7 devices support both JTAG and SWD transports.
-#
-source [find target/swj-dp.tcl]
-source [find mem_helper.tcl]
-
-if { [info exists CHIPNAME] } {
-   set _CHIPNAME $CHIPNAME
-} else {
-   set _CHIPNAME stm32h7x
-}
-
-set _ENDIAN little
-
-# Work-area is a space in RAM used for flash programming
-# By default use 64kB
-if { [info exists WORKAREASIZE] } {
-   set _WORKAREASIZE $WORKAREASIZE
-} else {
-   set _WORKAREASIZE 0x10000
-}
-
-#jtag scan chain
-if { [info exists CPUTAPID] } {
-   set _CPUTAPID $CPUTAPID
-} else {
-   if { [using_jtag] } {
-	  set _CPUTAPID 0x6ba00477
-   } {
-      set _CPUTAPID 0x6ba02477
-   }
-}
-
-swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
-
-if {[using_jtag]} {
- swj_newdap $_CHIPNAME bs -irlen 5
-}
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
-
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME stm32h7x 0x08000000 0 0 0 $_TARGETNAME
-
-# Clock after reset is HSI at 64 MHz, no need of PLL
-adapter_khz 1800
-
-adapter_nsrst_delay 100
-if {[using_jtag]} {
- jtag_ntrst_delay 100
-}
-
-# use hardware reset
-#
-# The STM32H7 does not support connect_assert_srst mode because the AXI is
-# unavailable while SRST is asserted, and that is used to access the DBGMCU
-# component at 0x5C001000 in the examine-end event handler.
-#
-# It is possible to access the DBGMCU component at 0xE00E1000 via AP2 instead
-# of the default AP0, and that works with SRST asserted; however, nonzero AP
-# usage does not work with HLA, so is not done by default. That change could be
-# made in a local configuration file if connect_assert_srst mode is needed for
-# a specific application and a non-HLA adapter is in use.
-reset_config srst_only srst_nogate
-
-if {![using_hla]} {
-   # if srst is not fitted use SYSRESETREQ to
-   # perform a soft reset
-   cortex_m reset_config sysresetreq
-
-   # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
-   # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
-   # makes the data access cacheable. This allows reading and writing data in the
-   # CPU cache from the debugger, which is far more useful than going straight to
-   # RAM when operating on typical variables, and is generally no worse when
-   # operating on special memory locations.
-   $_CHIPNAME.dap apcsw 0x08000000 0x08000000
-}
-
-$_TARGETNAME configure -event examine-end {
-	# Enable D3 and D1 DBG clocks
-	# DBGMCU_CR |= D3DBGCKEN | D1DBGCKEN
-	mmw 0x5C001004 0x00600000 0
-
-	# Enable debug during low power modes (uses more power)
-	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP in D3 & D1 Domains
-	mmw 0x5C001004 0x00000187 0
-
-	# Stop watchdog counters during halt
-	# DBGMCU_APB3FZ1 |= WWDG1
-	mmw 0x5C001034 0x00000040 0
-	# DBGMCU_APB4FZ1 |= WDGLSD1
-	mmw 0x5C001054 0x00040000 0
-}
-
-$_TARGETNAME configure -event trace-config {
-	# Set TRACECLKEN; TRACE_MODE is set to async; when using sync
-	# change this value accordingly to configure trace pins
-	# assignment
-	mmw 0x5C001004 0x00100000 0
-}
-
-$_TARGETNAME configure -event reset-init {
-	# Clock after reset is HSI at 64 MHz, no need of PLL
-	adapter_khz 4000
-}