From 2cd611de74de6e154abf949a478d55b52b5b2adc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Wed, 28 Jul 2021 11:50:28 +0000 Subject: [PATCH] qspi: bump spi speed to 100 MHz --- src/hardware/design_parameters.rs | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/hardware/design_parameters.rs b/src/hardware/design_parameters.rs index 4ac28e3..bd4cb30 100644 --- a/src/hardware/design_parameters.rs +++ b/src/hardware/design_parameters.rs @@ -11,13 +11,13 @@ pub const ADC_DAC_SCK_MAX: MegaHertz = MegaHertz(50); pub const TIMER_FREQUENCY: MegaHertz = MegaHertz(100); /// The QSPI frequency for communicating with the pounder DDS. -pub const POUNDER_QSPI_FREQUENCY: MegaHertz = MegaHertz(40); +pub const POUNDER_QSPI_FREQUENCY: MegaHertz = MegaHertz(100); /// The delay after initiating a QSPI transfer before asserting the IO_Update for the pounder DDS. -// Pounder Profile writes are always 16 bytes, with 2 cycles required per byte, coming out to a -// total of 32 QSPI clock cycles. The QSPI is configured for 40MHz, so this comes out to an offset -// of 800nS. We use 900ns to be safe. -pub const POUNDER_IO_UPDATE_DELAY: f32 = 900e-9; +// Pounder Profile writes are up to 16 bytes, with 2 cycles required per byte, coming out to a +// total of 32 QSPI clock cycles. The QSPI is configured for 100MHz, so this comes out to an offset +// of 320 ns. We use 400 ns to be safe. +pub const POUNDER_IO_UPDATE_DELAY: f32 = 400e-9; /// The duration to assert IO_Update for the pounder DDS. // IO_Update should be latched for 4 SYNC_CLK cycles after the QSPI profile write. With pounder