From dfe3ac877a538e753945e63a6a852a0f8c54ed5f Mon Sep 17 00:00:00 2001 From: Niklas Kuhrmeyer Date: Fri, 30 Oct 2020 12:16:28 +0100 Subject: [PATCH 01/18] added gateway --- src/main.rs | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/main.rs b/src/main.rs index 9e0c0ff..0f4b347 100644 --- a/src/main.rs +++ b/src/main.rs @@ -36,6 +36,8 @@ use stm32h7xx_hal::prelude::*; use embedded_hal::digital::v2::{InputPin, OutputPin}; use smoltcp as net; +use smoltcp::wire::Ipv4Address; +use smoltcp::iface::Routes; use stm32h7_ethernet as ethernet; use heapless::{consts::*, String}; @@ -76,6 +78,7 @@ mod build_info { pub struct NetStorage { ip_addrs: [net::wire::IpCidr; 1], neighbor_cache: [Option<(net::wire::IpAddress, net::iface::Neighbor)>; 8], + routes_storage: [Option<(smoltcp::wire::IpCidr, smoltcp::iface::Route)>; 2], } static mut NET_STORE: NetStorage = NetStorage { @@ -85,6 +88,8 @@ static mut NET_STORE: NetStorage = NetStorage { )], neighbor_cache: [None; 8], + + routes_storage: [None; 2], }; const SCALE: f32 = ((1 << 15) - 1) as f32; @@ -617,6 +622,10 @@ const APP: () = { 24, ); + let default_v4_gw = Ipv4Address::new(10,0,16,1); + let mut routes = Routes::new(&mut store.routes_storage[..]); + routes.add_default_ipv4_route(default_v4_gw).unwrap(); + let neighbor_cache = net::iface::NeighborCache::new(&mut store.neighbor_cache[..]); @@ -624,6 +633,7 @@ const APP: () = { .ethernet_addr(mac_addr) .neighbor_cache(neighbor_cache) .ip_addrs(&mut store.ip_addrs[..]) + .routes(routes) .finalize(); (interface, eth_mac) From 32d5e4dfe14161de6046792b5180e9565cc8b563 Mon Sep 17 00:00:00 2001 From: Niklas Kuhrmeyer Date: Fri, 30 Oct 2020 13:32:47 +0100 Subject: [PATCH 02/18] format --- src/main.rs | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/main.rs b/src/main.rs index 0f4b347..62ed019 100644 --- a/src/main.rs +++ b/src/main.rs @@ -36,8 +36,9 @@ use stm32h7xx_hal::prelude::*; use embedded_hal::digital::v2::{InputPin, OutputPin}; use smoltcp as net; -use smoltcp::wire::Ipv4Address; use smoltcp::iface::Routes; +use smoltcp::wire::Ipv4Address; + use stm32h7_ethernet as ethernet; use heapless::{consts::*, String}; @@ -622,7 +623,7 @@ const APP: () = { 24, ); - let default_v4_gw = Ipv4Address::new(10,0,16,1); + let default_v4_gw = Ipv4Address::new(10, 0, 16, 1); let mut routes = Routes::new(&mut store.routes_storage[..]); routes.add_default_ipv4_route(default_v4_gw).unwrap(); From 2f5d26aeaa7dd40a979918203a56e5791b40f9cd Mon Sep 17 00:00:00 2001 From: Niklas Kuhrmeyer Date: Fri, 30 Oct 2020 13:33:59 +0100 Subject: [PATCH 03/18] decreased routes_storage --- src/main.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main.rs b/src/main.rs index 62ed019..658bbd5 100644 --- a/src/main.rs +++ b/src/main.rs @@ -79,7 +79,7 @@ mod build_info { pub struct NetStorage { ip_addrs: [net::wire::IpCidr; 1], neighbor_cache: [Option<(net::wire::IpAddress, net::iface::Neighbor)>; 8], - routes_storage: [Option<(smoltcp::wire::IpCidr, smoltcp::iface::Route)>; 2], + routes_storage: [Option<(smoltcp::wire::IpCidr, smoltcp::iface::Route)>; 1], } static mut NET_STORE: NetStorage = NetStorage { @@ -90,7 +90,7 @@ static mut NET_STORE: NetStorage = NetStorage { neighbor_cache: [None; 8], - routes_storage: [None; 2], + routes_storage: [None; 1], }; const SCALE: f32 = ((1 << 15) - 1) as f32; From 2e9fdd9d4d0ae44059461ee0ef40274a8933ad66 Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Thu, 5 Nov 2020 08:06:42 +0100 Subject: [PATCH 04/18] Updating stm32h7xx-hal --- Cargo.lock | 74 +++--------------------------------------------------- Cargo.toml | 8 +----- 2 files changed, 5 insertions(+), 77 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index 998e749..014b427 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -335,37 +335,12 @@ dependencies = [ "cortex-m-semihosting", ] -[[package]] -name = "paste" -version = "0.1.18" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "45ca20c77d80be666aef2b45486da86238fabe33e38306bd3118fe4af33fa880" -dependencies = [ - "paste-impl", - "proc-macro-hack", -] - [[package]] name = "paste" version = "1.0.2" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "ba7ae1a2180ed02ddfdb5ab70c70d596a26dd642e097bb6fe78b1bde8588ed97" -[[package]] -name = "paste-impl" -version = "0.1.18" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "d95a7db200b97ef370c8e6de0088252f7e0dfff7d047a28528e47456c0fc98b6" -dependencies = [ - "proc-macro-hack", -] - -[[package]] -name = "proc-macro-hack" -version = "0.5.19" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "dbf0c48bc1d91375ae5c3cd81e3722dff1abcf81a30960240640d223f59fe0e5" - [[package]] name = "proc-macro2" version = "1.0.24" @@ -469,7 +444,6 @@ checksum = "0fe46639fd2ec79eadf8fe719f237a7a0bd4dac5d957f1ca5bbdbc1c3c39e53a" dependencies = [ "bitflags", "byteorder", - "log", "managed", ] @@ -494,8 +468,7 @@ dependencies = [ "serde", "serde-json-core", "smoltcp", - "stm32h7-ethernet", - "stm32h7xx-hal 0.8.0", + "stm32h7xx-hal", ] [[package]] @@ -504,17 +477,6 @@ version = "1.2.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "a8f112729512f8e442d81f95a8a7ddf2b7c6b8a1a6f509a95864142b30cab2d3" -[[package]] -name = "stm32h7" -version = "0.11.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "e9beb5e2a223c82f263c3051bba4614aebc6e98bd40217df3cd8817c83ac7bd8" -dependencies = [ - "bare-metal 0.2.5", - "cortex-m", - "vcell", -] - [[package]] name = "stm32h7" version = "0.12.1" @@ -527,38 +489,10 @@ dependencies = [ "vcell", ] -[[package]] -name = "stm32h7-ethernet" -version = "0.1.1" -source = "git+https://github.com/quartiq/stm32h7-ethernet.git#cf9b8bb2e1b440d8ada6ac6048f48dc4ed9c269a" -dependencies = [ - "cortex-m", - "log", - "smoltcp", - "stm32h7xx-hal 0.5.0", -] - -[[package]] -name = "stm32h7xx-hal" -version = "0.5.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "987c66628f30012ed9a41cc738421c5caece03292c0cc8fd1e99956f122735bd" -dependencies = [ - "bare-metal 0.2.5", - "cast", - "cortex-m", - "cortex-m-rt", - "embedded-hal", - "nb 0.1.3", - "paste 0.1.18", - "stm32h7 0.11.0", - "void", -] - [[package]] name = "stm32h7xx-hal" version = "0.8.0" -source = "git+https://github.com/quartiq/stm32h7xx-hal?branch=rs/issue-158/managed-spi#cc36bbbaa1bf21e53732cfc0f3dd7175c3ed6d44" +source = "git+https://github.com/stm32-rs/stm32h7xx-hal#cbb31d0b6d0c8530437367032a600a4ff74657f7" dependencies = [ "bare-metal 1.0.0", "cast", @@ -566,9 +500,9 @@ dependencies = [ "cortex-m-rt", "embedded-hal", "nb 1.0.0", - "paste 1.0.2", + "paste", "smoltcp", - "stm32h7 0.12.1", + "stm32h7", "void", ] diff --git a/Cargo.toml b/Cargo.toml index 0f2df5c..a57745e 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -52,15 +52,9 @@ default-features = false [dependencies.ad9959] path = "ad9959" -[dependencies.stm32h7-ethernet] -git = "https://github.com/quartiq/stm32h7-ethernet.git" -branch = "master" -features = ["stm32h743v"] - [dependencies.stm32h7xx-hal] features = ["stm32h743v", "rt", "unproven", "ethernet", "quadspi"] -git = "https://github.com/quartiq/stm32h7xx-hal" -branch = "rs/issue-158/managed-spi" +git = "https://github.com/stm32-rs/stm32h7xx-hal" [features] semihosting = ["panic-semihosting", "cortex-m-log/semihosting"] From f1ee9a2af54c245e1f10a9cdc9895b8febc4052e Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Thu, 5 Nov 2020 08:13:55 +0100 Subject: [PATCH 05/18] Adding CI support for PRs --- .github/workflows/ci.yml | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 124f429..40d2a76 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -2,10 +2,9 @@ name: Continuous Integration on: push: - branches: - - staging - - trying - - master + branches: [master, staging, trying] + pull_request: + branches: [master] env: CARGO_TERM_COLOR: always @@ -42,7 +41,7 @@ jobs: uses: actions-rs/cargo@v1 continue-on-error: true with: - command: clippy + command: clippy compile: runs-on: ubuntu-latest From c804312e605cd83c7fa526ca1ebaf4835c81dd98 Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Tue, 10 Nov 2020 15:13:57 +0100 Subject: [PATCH 06/18] Fixing deprecation warnings --- src/main.rs | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/main.rs b/src/main.rs index d75a16e..1c29522 100644 --- a/src/main.rs +++ b/src/main.rs @@ -1,3 +1,5 @@ +#![deny(warnings)] +#![allow(deprecated)] #![allow(clippy::missing_safety_doc)] #![no_std] #![no_main] From 7b86a2bc4218e4204303cd1f03f9d21bb811f2c0 Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Tue, 10 Nov 2020 15:14:49 +0100 Subject: [PATCH 07/18] Adding comment about deprecation allowance --- src/main.rs | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/main.rs b/src/main.rs index 1c29522..f453a49 100644 --- a/src/main.rs +++ b/src/main.rs @@ -1,5 +1,4 @@ #![deny(warnings)] -#![allow(deprecated)] #![allow(clippy::missing_safety_doc)] #![no_std] #![no_main] @@ -19,6 +18,9 @@ fn panic(_info: &core::panic::PanicInfo) -> ! { } } +// Deprecation warnings are temporarily allowed as the HAL DMA goes through updates. +#![allow(deprecated)] + #[cfg(feature = "semihosting")] extern crate panic_semihosting; From 84e31ef03640e279f787b3bb79c66258c50b935e Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Tue, 10 Nov 2020 15:16:37 +0100 Subject: [PATCH 08/18] Fixing directive position --- src/main.rs | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/main.rs b/src/main.rs index f453a49..642bd70 100644 --- a/src/main.rs +++ b/src/main.rs @@ -1,5 +1,9 @@ #![deny(warnings)] #![allow(clippy::missing_safety_doc)] + +// Deprecation warnings are temporarily allowed as the HAL DMA goes through updates. +#![allow(deprecated)] + #![no_std] #![no_main] #![cfg_attr(feature = "nightly", feature(asm))] @@ -18,9 +22,6 @@ fn panic(_info: &core::panic::PanicInfo) -> ! { } } -// Deprecation warnings are temporarily allowed as the HAL DMA goes through updates. -#![allow(deprecated)] - #[cfg(feature = "semihosting")] extern crate panic_semihosting; From a32ca39ca059d090669ddfd839b4233a79bb8d69 Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Tue, 10 Nov 2020 15:19:44 +0100 Subject: [PATCH 09/18] Removing spaces --- src/main.rs | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/main.rs b/src/main.rs index 642bd70..e628c31 100644 --- a/src/main.rs +++ b/src/main.rs @@ -1,9 +1,7 @@ #![deny(warnings)] #![allow(clippy::missing_safety_doc)] - // Deprecation warnings are temporarily allowed as the HAL DMA goes through updates. #![allow(deprecated)] - #![no_std] #![no_main] #![cfg_attr(feature = "nightly", feature(asm))] From f164a1a89e2ea54c06bacde5c64f988d6f9a92fb Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Tue, 10 Nov 2020 15:31:19 +0100 Subject: [PATCH 10/18] Update PR --- src/main.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main.rs b/src/main.rs index e628c31..a7d3d73 100644 --- a/src/main.rs +++ b/src/main.rs @@ -1,7 +1,7 @@ #![deny(warnings)] -#![allow(clippy::missing_safety_doc)] // Deprecation warnings are temporarily allowed as the HAL DMA goes through updates. #![allow(deprecated)] +#![allow(clippy::missing_safety_doc)] #![no_std] #![no_main] #![cfg_attr(feature = "nightly", feature(asm))] From 920d08c04cee6647d3919250f5871afa4488a33c Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 11 Nov 2020 15:22:47 +0800 Subject: [PATCH 11/18] update cargosha256 --- cargosha256.nix | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cargosha256.nix b/cargosha256.nix index ef00174..4da95a5 100644 --- a/cargosha256.nix +++ b/cargosha256.nix @@ -1 +1 @@ -"1626aw5ln581s1jzsf74y0djh715hdsjxzd3ck0xnb84a6kd4hkw" +"05b1xcr9jachnih0d6i63cfjcb88xrddmr2kf4h3vfwpjf8y9w10" From aa36446f954466aea094212b471662bb645b7a6d Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Wed, 11 Nov 2020 11:57:14 +0100 Subject: [PATCH 12/18] Adding updated docs for adc file --- Cargo.lock | 2 +- Cargo.toml | 4 +- src/adc.rs | 169 ++++++++++++++++++++++++++++++++++++++++++++-------- src/main.rs | 12 ++-- 4 files changed, 156 insertions(+), 31 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index 9f1bb5d..f247a6c 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -501,7 +501,7 @@ dependencies = [ [[package]] name = "stm32h7xx-hal" version = "0.8.0" -source = "git+https://github.com/quartiq/stm32h7xx-hal?branch=feature/stabilizer-dma#5fbbfa9352f720994c210e5c21601f3acf9dc40c" +source = "git+https://github.com/quartiq/stm32h7xx-hal?branch=feature/dma-rtic-example#d8cb6fa5099282665f5e5068a9dcdc9ebaa63240" dependencies = [ "bare-metal 1.0.0", "cast", diff --git a/Cargo.toml b/Cargo.toml index 04bd4e5..049e61c 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -55,7 +55,7 @@ path = "ad9959" [dependencies.stm32h7xx-hal] features = ["stm32h743v", "rt", "unproven", "ethernet", "quadspi"] git = "https://github.com/quartiq/stm32h7xx-hal" -branch = "feature/stabilizer-dma" +branch = "feature/dma-rtic-example" [features] semihosting = ["panic-semihosting", "cortex-m-log/semihosting"] @@ -65,7 +65,7 @@ nightly = ["cortex-m/inline-asm"] [profile.dev] codegen-units = 1 incremental = false -opt-level = 1 +opt-level = 3 [profile.release] opt-level = 3 diff --git a/src/adc.rs b/src/adc.rs index cb15c27..039a7c3 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -1,13 +1,36 @@ +///! Stabilizer ADC management interface +///! +///! The Stabilizer ADCs utilize a DMA channel to trigger sampling. The SPI streams are configured +///! for full-duplex operation, but only RX is connected to physical pins. A timer channel is +///! configured to generate a DMA write into the SPI TXFIFO, which initiates a SPI transfer and +///! results in an ADC sample read for both channels. +///! +///! In order to read multiple samples without interrupting the CPU, a separate DMA transfer is +///! configured to read from each of the ADC SPI RX FIFOs. Due to the design of the SPI peripheral, +///! these DMA transfers stall when no data is available in the FIFO. Thus, the DMA transfer only +///! completes after all samples have been read. When this occurs, a CPU interrupt is generated so +///! that software can process the acquired samples from both ADCs. Only one of the ADC DMA streams +///! is configured to generate an interrupt to handle both transfers, so it is necessary to ensure +///! both transfers are completed before reading the data. This is usually not significant for +///! busy-waiting because the transfers should complete at approximately the same time. use super::{ - hal, DMAReq, DmaConfig, MemoryToPeripheral, PeripheralToMemory, Priority, - Stream, TargetAddress, Transfer, + hal, DMAReq, DmaConfig, MemoryToPeripheral, PeripheralToMemory, Priority, TargetAddress, + Transfer, }; +// The desired ADC input buffer size. This is use configurable. const INPUT_BUFFER_SIZE: usize = 1; +// The following data is written by the timer ADC sample trigger into each of the SPI TXFIFOs. Note +// that because the SPI MOSI line is not connected, this data is dont-care. Data in AXI SRAM is not +// initialized on boot, so the contents are random. #[link_section = ".axisram.buffers"] static mut SPI_START: [u16; 1] = [0x00]; +// The following global buffers are used for the ADC sample DMA transfers. Two buffers are used for +// each transfer in a ping-pong buffer configuration (one is being acquired while the other is being +// processed). Note that the contents of AXI SRAM is uninitialized, so the buffer contents on +// startup are undefined. #[link_section = ".axisram.buffers"] static mut ADC0_BUF0: [u16; INPUT_BUFFER_SIZE] = [0; INPUT_BUFFER_SIZE]; @@ -20,8 +43,9 @@ static mut ADC1_BUF0: [u16; INPUT_BUFFER_SIZE] = [0; INPUT_BUFFER_SIZE]; #[link_section = ".axisram.buffers"] static mut ADC1_BUF1: [u16; INPUT_BUFFER_SIZE] = [0; INPUT_BUFFER_SIZE]; +/// SPI2 is used as a ZST (zero-sized type) for indicating a DMA transfer into the SPI2 TX FIFO +/// whenever the tim2 update dma request occurs. struct SPI2 {} - impl SPI2 { pub fn new() -> Self { Self {} @@ -29,18 +53,23 @@ impl SPI2 { } unsafe impl TargetAddress for SPI2 { + /// SPI2 is configured to operate using 16-bit transfer words. type MemSize = u16; - const REQUEST_LINE: Option = Some(DMAReq::TIM2_UP as u8); + /// SPI2 DMA requests are generated whenever TIM2 CH1 comparison occurs. + const REQUEST_LINE: Option = Some(DMAReq::TIM2_CH1 as u8); + /// Whenever the DMA request occurs, it should write into SPI2's TX FIFO to start a DMA + /// transfer. fn address(&self) -> u32 { let regs = unsafe { &*hal::stm32::SPI2::ptr() }; ®s.txdr as *const _ as u32 } } +/// SPI3 is used as a ZST (zero-sized type) for indicating a DMA transfer into the SPI3 TX FIFO +/// whenever the tim2 update dma request occurs. struct SPI3 {} - impl SPI3 { pub fn new() -> Self { Self {} @@ -48,26 +77,37 @@ impl SPI3 { } unsafe impl TargetAddress for SPI3 { + /// SPI3 is configured to operate using 16-bit transfer words. type MemSize = u16; - const REQUEST_LINE: Option = Some(DMAReq::TIM2_UP as u8); + /// SPI3 DMA requests are generated whenever TIM2 CH2 comparison occurs. + const REQUEST_LINE: Option = Some(DMAReq::TIM2_CH2 as u8); + /// Whenever the DMA request occurs, it should write into SPI3's TX FIFO to start a DMA + /// transfer. fn address(&self) -> u32 { let regs = unsafe { &*hal::stm32::SPI3::ptr() }; ®s.txdr as *const _ as u32 } } +/// Represents both ADC input channels. pub struct AdcInputs { adc0: Adc0Input, adc1: Adc1Input, } impl AdcInputs { + /// Construct the ADC inputs. pub fn new(adc0: Adc0Input, adc1: Adc1Input) -> Self { Self { adc0, adc1 } } + /// Interrupt handler to handle when the sample collection DMA transfer completes. + /// + /// # Returns + /// (adc0, adc1) where adcN is a reference to the collected ADC samples. Two array references + /// are returned - one for each ADC sample stream. pub fn transfer_complete_handler( &mut self, ) -> (&[u16; INPUT_BUFFER_SIZE], &[u16; INPUT_BUFFER_SIZE]) { @@ -77,6 +117,7 @@ impl AdcInputs { } } +/// Represents data associated with ADC0. pub struct Adc0Input { next_buffer: Option<&'static mut [u16; INPUT_BUFFER_SIZE]>, transfer: Transfer< @@ -85,72 +126,113 @@ pub struct Adc0Input { PeripheralToMemory, &'static mut [u16; INPUT_BUFFER_SIZE], >, + _trigger_transfer: Transfer< + hal::dma::dma::Stream0, + SPI2, + MemoryToPeripheral, + &'static mut [u16; 1], + >, } impl Adc0Input { + /// Construct the ADC0 input channel. + /// + /// # Args + /// * `spi` - The SPI interface used to communicate with the ADC. + /// * `trigger_stream` - The DMA stream used to trigger each ADC transfer by writing a word into + /// the SPI TX FIFO. + /// * `data_stream` - The DMA stream used to read samples received over SPI into a data buffer. pub fn new( spi: hal::spi::Spi, trigger_stream: hal::dma::dma::Stream0, data_stream: hal::dma::dma::Stream1, ) -> Self { + // The trigger stream constantly writes to the TX FIFO using a static word (dont-care + // contents). Thus, neither the memory or peripheral address ever change. This is run in + // circular mode to be completed at every DMA request. let trigger_config = DmaConfig::default() .memory_increment(false) .peripheral_increment(false) .priority(Priority::High) .circular_buffer(true); + // Construct the trigger stream to write from memory to the peripheral. let mut trigger_transfer: Transfer<_, _, MemoryToPeripheral, _> = Transfer::init( trigger_stream, - &SPI2::new(), + SPI2::new(), unsafe { &mut SPI_START }, None, trigger_config, ); + // The data stream constantly reads from the SPI RX FIFO into a RAM buffer. The peripheral + // stalls reads of the SPI RX FIFO until data is available, so the DMA transfer completes + // after the requested number of samples have been collected. Note that only ADC1's data + // stream is used to trigger a transfer completion interrupt. let data_config = DmaConfig::default() .memory_increment(true) .priority(Priority::VeryHigh) .peripheral_increment(false); + // A SPI peripheral error interrupt is used to determine if the RX FIFO overflows. This + // indicates that samples were dropped due to excessive processing time in the main + // application (e.g. a second DMA transfer completes before the first was done with + // processing). This is used as a flow control indicator to guarantee that no ADC samples + // are lost. let mut spi = spi.disable(); spi.listen(hal::spi::Event::Error); + // The data transfer is always a transfer of data from the peripheral to a RAM buffer. let mut data_transfer: Transfer<_, _, PeripheralToMemory, _> = Transfer::init( data_stream, - &spi, + spi, unsafe { &mut ADC0_BUF0 }, None, data_config, ); - spi.enable_dma_rx(); - spi.enable_dma_tx(); + data_transfer.start(|spi| { + // Allow the SPI FIFOs to operate using only DMA data channels. + spi.enable_dma_rx(); + spi.enable_dma_tx(); - let spi = spi.enable(); - spi.inner().cr1.modify(|_, w| w.cstart().started()); + // Enable SPI and start it in infinite transaction mode. + spi.inner().cr1.modify(|_, w| w.spe().set_bit()); + spi.inner().cr1.modify(|_, w| w.cstart().started()); + }); - data_transfer.start(); - trigger_transfer.start(); + trigger_transfer.start(|_| {}); Self { next_buffer: unsafe { Some(&mut ADC0_BUF1) }, transfer: data_transfer, + _trigger_transfer: trigger_transfer, } } + /// Handle a transfer completion. + /// + /// # Returns + /// A reference to the underlying buffer that has been filled with ADC samples. pub fn transfer_complete_handler(&mut self) -> &[u16; INPUT_BUFFER_SIZE] { let next_buffer = self.next_buffer.take().unwrap(); - while hal::dma::dma::Stream1::::is_enabled() {} + + // Wait for the transfer to fully complete before continuing. + while self.transfer.get_transfer_complete_flag() == false {} + + // Start the next transfer. self.transfer.clear_interrupts(); let (prev_buffer, _) = self.transfer.next_transfer(next_buffer).unwrap(); + self.next_buffer.replace(prev_buffer); self.next_buffer.as_ref().unwrap() } } +/// Represents the data input stream from ADC1 pub struct Adc1Input { next_buffer: Option<&'static mut [u16; INPUT_BUFFER_SIZE]>, transfer: Transfer< @@ -159,68 +241,107 @@ pub struct Adc1Input { PeripheralToMemory, &'static mut [u16; INPUT_BUFFER_SIZE], >, + _trigger_transfer: Transfer< + hal::dma::dma::Stream2, + SPI3, + MemoryToPeripheral, + &'static mut [u16; 1], + >, } impl Adc1Input { + /// Construct a new ADC1 input data stream. + /// + /// # Args + /// * `spi` - The SPI interface connected to ADC1. + /// * `trigger_stream` - The DMA stream used to trigger ADC conversions on the SPI interface. + /// * `data_stream` - The DMA stream used to read ADC samples from the SPI RX FIFO. pub fn new( spi: hal::spi::Spi, trigger_stream: hal::dma::dma::Stream2, data_stream: hal::dma::dma::Stream3, ) -> Self { + // The trigger stream constantly writes to the TX FIFO using a static word (dont-care + // contents). Thus, neither the memory or peripheral address ever change. This is run in + // circular mode to be completed at every DMA request. let trigger_config = DmaConfig::default() .memory_increment(false) .peripheral_increment(false) .priority(Priority::High) .circular_buffer(true); + // Construct the trigger stream to write from memory to the peripheral. let mut trigger_transfer: Transfer<_, _, MemoryToPeripheral, _> = Transfer::init( trigger_stream, - &SPI3::new(), + SPI3::new(), unsafe { &mut SPI_START }, None, trigger_config, ); + // The data stream constantly reads from the SPI RX FIFO into a RAM buffer. The peripheral + // stalls reads of the SPI RX FIFO until data is available, so the DMA transfer completes + // after the requested number of samples have been collected. Note that only ADC1's data + // stream is used to trigger a transfer completion interrupt. let data_config = DmaConfig::default() .memory_increment(true) .transfer_complete_interrupt(true) .priority(Priority::VeryHigh) .peripheral_increment(false); + // A SPI peripheral error interrupt is used to determine if the RX FIFO overflows. This + // indicates that samples were dropped due to excessive processing time in the main + // application (e.g. a second DMA transfer completes before the first was done with + // processing). This is used as a flow control indicator to guarantee that no ADC samples + // are lost. let mut spi = spi.disable(); spi.listen(hal::spi::Event::Error); + // The data transfer is always a transfer of data from the peripheral to a RAM buffer. let mut data_transfer: Transfer<_, _, PeripheralToMemory, _> = Transfer::init( data_stream, - &spi, + spi, unsafe { &mut ADC1_BUF0 }, None, data_config, ); - spi.enable_dma_rx(); - spi.enable_dma_tx(); + data_transfer.start(|spi| { + // Allow the SPI FIFOs to operate using only DMA data channels. + spi.enable_dma_rx(); + spi.enable_dma_tx(); - let spi = spi.enable(); - spi.inner().cr1.modify(|_, w| w.cstart().started()); + // Enable SPI and start it in infinite transaction mode. + spi.inner().cr1.modify(|_, w| w.spe().set_bit()); + spi.inner().cr1.modify(|_, w| w.cstart().started()); + }); - data_transfer.start(); - trigger_transfer.start(); + trigger_transfer.start(|_| {}); Self { next_buffer: unsafe { Some(&mut ADC1_BUF1) }, transfer: data_transfer, + _trigger_transfer: trigger_transfer, } } + /// Handle a transfer completion. + /// + /// # Returns + /// A reference to the underlying buffer that has been filled with ADC samples. pub fn transfer_complete_handler(&mut self) -> &[u16; INPUT_BUFFER_SIZE] { let next_buffer = self.next_buffer.take().unwrap(); - while hal::dma::dma::Stream3::::is_enabled() {} + + // Wait for the transfer to fully complete before continuing. + while self.transfer.get_transfer_complete_flag() == false {} + + // Start the next transfer. self.transfer.clear_interrupts(); let (prev_buffer, _) = self.transfer.next_transfer(next_buffer).unwrap(); + self.next_buffer.replace(prev_buffer); self.next_buffer.as_ref().unwrap() } diff --git a/src/main.rs b/src/main.rs index 3a0b00e..b7cf7db 100644 --- a/src/main.rs +++ b/src/main.rs @@ -1,6 +1,4 @@ #![deny(warnings)] -// Deprecation warnings are temporarily allowed as the HAL DMA goes through updates. -#![allow(deprecated)] #![allow(clippy::missing_safety_doc)] #![no_std] #![no_main] @@ -41,7 +39,7 @@ use hal::{ dma::{ config::Priority, dma::{DMAReq, DmaConfig}, - traits::{Stream, TargetAddress}, + traits::TargetAddress, MemoryToPeripheral, PeripheralToMemory, Transfer, }, ethernet::{self, PHY}, @@ -706,8 +704,14 @@ const APP: () = { &ccdr.clocks, ); { + // Listen to the CH1 and CH2 comparison events. These channels should have a value of + // zero loaded into them, so the event should occur whenever the timer overflows. Note + // that we use channels instead of timer updates because each SPI DMA transfer needs a + // unique request line. let t2_regs = unsafe { &*hal::stm32::TIM2::ptr() }; - t2_regs.dier.modify(|_, w| w.ude().set_bit()); + t2_regs + .dier + .modify(|_, w| w.cc1de().set_bit().cc2de().set_bit()); } init::LateResources { From 8f399ec12b6b5bc9cd8bae3ae51f0bd3c02227fb Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Wed, 11 Nov 2020 11:57:57 +0100 Subject: [PATCH 13/18] Reverting openocd change --- openocd.gdb | 3 --- 1 file changed, 3 deletions(-) diff --git a/openocd.gdb b/openocd.gdb index c1ae67a..e903a33 100644 --- a/openocd.gdb +++ b/openocd.gdb @@ -26,6 +26,3 @@ set var $t0=*$cc continue end #set var $t0=*$cc - -source ../../PyCortexMDebug/cmdebug/svd_gdb.py -svd_load ~/Downloads/STM32H743x.svd From 3088a002c015e56eb2e4535e6f8cf1927b9523e7 Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Wed, 11 Nov 2020 12:09:27 +0100 Subject: [PATCH 14/18] Adding documentation --- src/adc.rs | 4 ++-- src/dac.rs | 58 ++++++++++++++++++++++++++++++++++++++++++++++++++--- src/main.rs | 10 +++++++++ 3 files changed, 67 insertions(+), 5 deletions(-) diff --git a/src/adc.rs b/src/adc.rs index 039a7c3..e3310f4 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -14,8 +14,8 @@ ///! both transfers are completed before reading the data. This is usually not significant for ///! busy-waiting because the transfers should complete at approximately the same time. use super::{ - hal, DMAReq, DmaConfig, MemoryToPeripheral, PeripheralToMemory, Priority, TargetAddress, - Transfer, + hal, DMAReq, DmaConfig, MemoryToPeripheral, PeripheralToMemory, Priority, + TargetAddress, Transfer, }; // The desired ADC input buffer size. This is use configurable. diff --git a/src/dac.rs b/src/dac.rs index d2b36a3..8829385 100644 --- a/src/dac.rs +++ b/src/dac.rs @@ -1,21 +1,44 @@ +///! Stabilizer DAC output control +///! +///! Stabilizer output DACs do not currently rely on DMA requests for generating output. +///! Instead, the DACs utilize an internal queue for storing output codes. A timer then periodically +///! generates an interrupt which triggers an update of the DACs via a write over SPI. use super::hal; use heapless::consts; +/// Controller structure for managing the DAC outputs. pub struct DacOutputs { dac0_spi: hal::spi::Spi, dac1_spi: hal::spi::Spi, - outputs: heapless::spsc::Queue<(u16, u16), consts::U32>, timer: hal::timer::Timer, + + // The queue is provided a default length of 32 updates, but this queue can be updated by the + // end user to be larger if necessary. + outputs: heapless::spsc::Queue<(u16, u16), consts::U32>, } impl DacOutputs { + /// Construct a new set of DAC output controls + /// + /// # Args + /// * `dac0_spi` - The SPI interface to the DAC0 output. + /// * `dac1_spi` - The SPI interface to the DAC1 output. + /// * `timer` - The timer used to generate periodic events for updating the DACs. pub fn new( - dac0_spi: hal::spi::Spi, - dac1_spi: hal::spi::Spi, + mut dac0_spi: hal::spi::Spi, + mut dac1_spi: hal::spi::Spi, mut timer: hal::timer::Timer, ) -> Self { + // Start the DAC SPI interfaces in infinite transaction mode. CS is configured in + // auto-suspend mode. dac0_spi.inner().cr1.modify(|_, w| w.cstart().started()); dac1_spi.inner().cr1.modify(|_, w| w.cstart().started()); + + dac0_spi.listen(hal::spi::Event::Error); + dac1_spi.listen(hal::spi::Event::Error); + + // Stop the timer and begin listening for timeouts. Timeouts will be used as a means to + // generate new DAC outputs. timer.pause(); timer.reset_counter(); timer.clear_irq(); @@ -29,11 +52,28 @@ impl DacOutputs { } } + /// Push a set of new DAC output codes to the internal queue. + /// + /// # Note + /// The earlier DAC output codes will be generated within 1 update cycle of the codes. This is a + /// fixed latency currently. + /// + /// This function will panic if too many codes are written. + /// + /// # Args + /// * `dac0_value` - The value to enqueue for a DAC0 update. + /// * `dac1_value` - The value to enqueue for a DAC1 update. pub fn push(&mut self, dac0_value: u16, dac1_value: u16) { self.outputs.enqueue((dac0_value, dac1_value)).unwrap(); self.timer.resume(); } + /// Update the DAC codes with the next set of values in the internal queue. + /// + /// # Note + /// This is intended to be called from the TIM3 update ISR. + /// + /// If the last value in the queue is used, the timer is stopped. pub fn update(&mut self) { self.timer.clear_irq(); match self.outputs.dequeue() { @@ -46,7 +86,19 @@ impl DacOutputs { }; } + /// Write immediate values to the DAC outputs. + /// + /// # Note + /// The DACs will be updated as soon as the SPI transfer completes, which will be nominally + /// 320nS after this function call. + /// + /// # Args + /// * `dac0_value` - The output code to write to DAC0. + /// * `dac1_value` - The output code to write to DAC1. pub fn write(&mut self, dac0_value: u16, dac1_value: u16) { + // In order to optimize throughput and minimize latency, the DAC codes are written directly + // into the SPI TX FIFO. No error checking is conducted. Errors are handled via interrupts + // instead. unsafe { core::ptr::write_volatile( &self.dac0_spi.inner().txdr as *const _ as *mut u16, diff --git a/src/main.rs b/src/main.rs index b7cf7db..b5fff64 100644 --- a/src/main.rs +++ b/src/main.rs @@ -954,6 +954,16 @@ const APP: () = { panic!("ADC0 input overrun"); } + #[task(binds = SPI4, priority = 1)] + fn spi4(_: spi4::Context) { + panic!("DAC0 output error"); + } + + #[task(binds = SPI5, priority = 1)] + fn spi5(_: spi5::Context) { + panic!("DAC1 output error"); + } + extern "C" { // hw interrupt handlers for RTIC to use for scheduling tasks // one per priority From da9ca818563511c33586ff3c71a4431e06bf798b Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Wed, 11 Nov 2020 12:12:19 +0100 Subject: [PATCH 15/18] Reverting changeset --- src/iir.rs | 10 ---------- src/main.rs | 16 ++++++++++++---- 2 files changed, 12 insertions(+), 14 deletions(-) diff --git a/src/iir.rs b/src/iir.rs index ff2d011..0c34306 100644 --- a/src/iir.rs +++ b/src/iir.rs @@ -105,14 +105,4 @@ impl IIR { xy[xy.len() / 2] = y0; y0 } - - pub fn update_from_adc_sample( - &mut self, - sample: u16, - state: &mut IIRState, - ) -> u16 { - let x0 = f32::from(sample as i16); - let y0 = self.update(state, x0); - y0 as i16 as u16 ^ 0x8000 - } } diff --git a/src/main.rs b/src/main.rs index b5fff64..1805370 100644 --- a/src/main.rs +++ b/src/main.rs @@ -742,11 +742,19 @@ const APP: () = { c.resources.adcs.transfer_complete_handler(); for (adc0, adc1) in adc0_samples.iter().zip(adc1_samples.iter()) { - let result_adc0 = c.resources.iir_ch[0] - .update_from_adc_sample(*adc0, &mut c.resources.iir_state[0]); + let result_adc0 = { + let x0 = f32::from(*adc0 as i16); + let y0 = c.resources.iir_ch[0] + .update(&mut c.resources.iir_state[0], x0); + y0 as i16 as u16 ^ 0x8000 + }; - let result_adc1 = c.resources.iir_ch[1] - .update_from_adc_sample(*adc1, &mut c.resources.iir_state[1]); + let result_adc1 = { + let x1 = f32::from(*adc1 as i16); + let y1 = c.resources.iir_ch[1] + .update(&mut c.resources.iir_state[1], x1); + y1 as i16 as u16 ^ 0x8000 + }; c.resources .dacs From 3b953e36aa3ec77ee00de4c70830f196301971b5 Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Wed, 11 Nov 2020 18:42:34 +0100 Subject: [PATCH 16/18] Adding compile-time management of TIM2 channels --- src/adc.rs | 18 ++++++++++++++++-- src/main.rs | 46 +++++++++++++++++++++++++--------------------- 2 files changed, 41 insertions(+), 23 deletions(-) diff --git a/src/adc.rs b/src/adc.rs index e3310f4..d63ebe9 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -14,8 +14,8 @@ ///! both transfers are completed before reading the data. This is usually not significant for ///! busy-waiting because the transfers should complete at approximately the same time. use super::{ - hal, DMAReq, DmaConfig, MemoryToPeripheral, PeripheralToMemory, Priority, - TargetAddress, Transfer, + hal, sampling_timer, DMAReq, DmaConfig, MemoryToPeripheral, + PeripheralToMemory, Priority, TargetAddress, Transfer, }; // The desired ADC input buffer size. This is use configurable. @@ -142,11 +142,18 @@ impl Adc0Input { /// * `trigger_stream` - The DMA stream used to trigger each ADC transfer by writing a word into /// the SPI TX FIFO. /// * `data_stream` - The DMA stream used to read samples received over SPI into a data buffer. + /// * `_trigger_channel` - The ADC sampling timer output compare channel for read triggers. pub fn new( spi: hal::spi::Spi, trigger_stream: hal::dma::dma::Stream0, data_stream: hal::dma::dma::Stream1, + trigger_channel: sampling_timer::Timer2Channel1, ) -> Self { + // Generate DMA events when an output compare of the timer hitting zero (timer roll over) + // occurs. + trigger_channel.listen_dma(); + trigger_channel.to_output_compare(0); + // The trigger stream constantly writes to the TX FIFO using a static word (dont-care // contents). Thus, neither the memory or peripheral address ever change. This is run in // circular mode to be completed at every DMA request. @@ -256,11 +263,18 @@ impl Adc1Input { /// * `spi` - The SPI interface connected to ADC1. /// * `trigger_stream` - The DMA stream used to trigger ADC conversions on the SPI interface. /// * `data_stream` - The DMA stream used to read ADC samples from the SPI RX FIFO. + /// * `trigger_channel` - The ADC sampling timer output compare channel for read triggers. pub fn new( spi: hal::spi::Spi, trigger_stream: hal::dma::dma::Stream2, data_stream: hal::dma::dma::Stream3, + trigger_channel: sampling_timer::Timer2Channel2, ) -> Self { + // Generate DMA events when an output compare of the timer hitting zero (timer roll over) + // occurs. + trigger_channel.listen_dma(); + trigger_channel.to_output_compare(0); + // The trigger stream constantly writes to the TX FIFO using a static word (dont-care // contents). Thus, neither the memory or peripheral address ever change. This is run in // circular mode to be completed at every DMA request. diff --git a/src/main.rs b/src/main.rs index 1805370..59b19fc 100644 --- a/src/main.rs +++ b/src/main.rs @@ -62,6 +62,7 @@ mod dac; mod eeprom; mod iir; mod pounder; +mod sampling_timer; mod server; use adc::{Adc0Input, Adc1Input, AdcInputs}; @@ -187,8 +188,6 @@ const APP: () = { eeprom_i2c: hal::i2c::I2c, - timer: hal::timer::Timer, - // Note: It appears that rustfmt generates a format that GDB cannot recognize, which // results in GDB breakpoints being set improperly. #[rustfmt::skip] @@ -264,6 +263,16 @@ const APP: () = { let dma_streams = hal::dma::dma::StreamsTuple::new(dp.DMA1, ccdr.peripheral.DMA1); + // Configure timer 2 to trigger conversions for the ADC + let timer2 = dp.TIM2.timer( + SAMPLE_FREQUENCY_KHZ.khz(), + ccdr.peripheral.TIM2, + &ccdr.clocks, + ); + + let mut sampling_timer = sampling_timer::SamplingTimer::new(timer2); + let sampling_timer_channels = sampling_timer.channels(); + // Configure the SPI interfaces to the ADCs and DACs. let adcs = { let adc0 = { @@ -296,7 +305,12 @@ const APP: () = { &ccdr.clocks, ); - Adc0Input::new(spi, dma_streams.0, dma_streams.1) + Adc0Input::new( + spi, + dma_streams.0, + dma_streams.1, + sampling_timer_channels.ch1, + ) }; let adc1 = { @@ -329,7 +343,12 @@ const APP: () = { &ccdr.clocks, ); - Adc1Input::new(spi, dma_streams.2, dma_streams.3) + Adc1Input::new( + spi, + dma_streams.2, + dma_streams.3, + sampling_timer_channels.ch2, + ) }; AdcInputs::new(adc0, adc1) @@ -697,22 +716,8 @@ const APP: () = { // Utilize the cycle counter for RTIC scheduling. cp.DWT.enable_cycle_counter(); - // Configure timer 2 to trigger conversions for the ADC - let timer2 = dp.TIM2.timer( - SAMPLE_FREQUENCY_KHZ.khz(), - ccdr.peripheral.TIM2, - &ccdr.clocks, - ); - { - // Listen to the CH1 and CH2 comparison events. These channels should have a value of - // zero loaded into them, so the event should occur whenever the timer overflows. Note - // that we use channels instead of timer updates because each SPI DMA transfer needs a - // unique request line. - let t2_regs = unsafe { &*hal::stm32::TIM2::ptr() }; - t2_regs - .dier - .modify(|_, w| w.cc1de().set_bit().cc2de().set_bit()); - } + // Start sampling ADCs. + sampling_timer.start(); init::LateResources { afe0: afe0, @@ -721,7 +726,6 @@ const APP: () = { adcs, dacs, - timer: timer2, pounder: pounder_devices, eeprom_i2c, From 56bcf1e0aad89a6f9bc4c240ce2cb94ea113c51f Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Wed, 11 Nov 2020 18:44:28 +0100 Subject: [PATCH 17/18] Adding sampling_timer file --- src/sampling_timer.rs | 107 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 107 insertions(+) create mode 100644 src/sampling_timer.rs diff --git a/src/sampling_timer.rs b/src/sampling_timer.rs new file mode 100644 index 0000000..b412b75 --- /dev/null +++ b/src/sampling_timer.rs @@ -0,0 +1,107 @@ +///! The sampling timer is used for managing ADC sampling and external reference timestamping. +use super::hal; + +pub use hal::stm32::tim2::ccmr2_input::CC4S_A; + +/// The timer used for managing ADC sampling. +pub struct SamplingTimer { + timer: hal::timer::Timer, + channels: Option, +} + +impl SamplingTimer { + /// Construct the sampling timer. + pub fn new(mut timer: hal::timer::Timer) -> Self { + timer.pause(); + + Self { + timer, + channels: Some(TimerChannels::new()), + } + } + + /// Get the timer capture/compare channels. + pub fn channels(&mut self) -> TimerChannels { + self.channels.take().unwrap() + } + + /// Start the sampling timer. + pub fn start(&mut self) { + self.timer.reset_counter(); + self.timer.resume(); + } +} + +/// The capture/compare channels for the sampling timer. +/// +/// # Note +/// This should not be instantiated directly. +pub struct TimerChannels { + pub ch1: Timer2Channel1, + pub ch2: Timer2Channel2, + pub ch3: Timer2Channel3, + pub ch4: Timer2Channel4, +} + +impl TimerChannels { + fn new() -> Self { + Self { + ch1: Timer2Channel1 {}, + ch2: Timer2Channel2 {}, + ch3: Timer2Channel3 {}, + ch4: Timer2Channel4 {}, + } + } +} + +/// Representation of CH1 of TIM2. +pub struct Timer2Channel1 {} + +impl Timer2Channel1 { + /// Allow CH1 to generate DMA requests. + pub fn listen_dma(&self) { + let regs = unsafe { &*hal::stm32::TIM2::ptr() }; + regs.dier.modify(|_, w| w.cc1de().set_bit()); + } + + /// Operate CH1 as an output-compare. + /// + /// # Args + /// * `value` - The value to compare the sampling timer's counter against. + pub fn to_output_compare(&self, value: u32) { + let regs = unsafe { &*hal::stm32::TIM2::ptr() }; + assert!(value <= regs.arr.read().bits()); + regs.ccr1.write(|w| w.ccr().bits(value)); + regs.ccmr1_output() + .modify(|_, w| unsafe { w.cc1s().bits(0) }); + } +} + +/// Representation of CH2 of TIM2. +pub struct Timer2Channel2 {} + +impl Timer2Channel2 { + /// Allow CH2 to generate DMA requests. + pub fn listen_dma(&self) { + let regs = unsafe { &*hal::stm32::TIM2::ptr() }; + regs.dier.modify(|_, w| w.cc2de().set_bit()); + } + + /// Operate CH2 as an output-compare. + /// + /// # Args + /// * `value` - The value to compare the sampling timer's counter against. + pub fn to_output_compare(&self, value: u32) { + let regs = unsafe { &*hal::stm32::TIM2::ptr() }; + assert!(value <= regs.arr.read().bits()); + regs.ccr2.write(|w| w.ccr().bits(value)); + regs.ccmr1_output() + .modify(|_, w| unsafe { w.cc2s().bits(0) }); + } +} + +/// Representation of CH3 of TIM2. +pub struct Timer2Channel3 {} + +/// Representation of CH4 of TIM2. +pub struct Timer2Channel4 {} From 91809cf255eff81b86c5c5e530e8a0c9d1ab13fb Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Fri, 13 Nov 2020 10:47:44 +0100 Subject: [PATCH 18/18] Adding DMA support for DAC writes --- Cargo.lock | 2 +- Cargo.toml | 4 +- src/adc.rs | 27 ++-- src/dac.rs | 369 ++++++++++++++++++++++++++++++------------ src/main.rs | 46 +++--- src/sampling_timer.rs | 40 +++++ 6 files changed, 348 insertions(+), 140 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index f247a6c..3c96c4f 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -501,7 +501,7 @@ dependencies = [ [[package]] name = "stm32h7xx-hal" version = "0.8.0" -source = "git+https://github.com/quartiq/stm32h7xx-hal?branch=feature/dma-rtic-example#d8cb6fa5099282665f5e5068a9dcdc9ebaa63240" +source = "git+https://github.com/stm32-rs/stm32h7xx-hal?branch=dma#0bfeeca4ce120c1b7c6d140a7da73a4372b874d8" dependencies = [ "bare-metal 1.0.0", "cast", diff --git a/Cargo.toml b/Cargo.toml index 049e61c..429fe85 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -54,8 +54,8 @@ path = "ad9959" [dependencies.stm32h7xx-hal] features = ["stm32h743v", "rt", "unproven", "ethernet", "quadspi"] -git = "https://github.com/quartiq/stm32h7xx-hal" -branch = "feature/dma-rtic-example" +git = "https://github.com/stm32-rs/stm32h7xx-hal" +branch = "dma" [features] semihosting = ["panic-semihosting", "cortex-m-log/semihosting"] diff --git a/src/adc.rs b/src/adc.rs index d63ebe9..55ed2a8 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -15,12 +15,9 @@ ///! busy-waiting because the transfers should complete at approximately the same time. use super::{ hal, sampling_timer, DMAReq, DmaConfig, MemoryToPeripheral, - PeripheralToMemory, Priority, TargetAddress, Transfer, + PeripheralToMemory, Priority, TargetAddress, Transfer, SAMPLE_BUFFER_SIZE, }; -// The desired ADC input buffer size. This is use configurable. -const INPUT_BUFFER_SIZE: usize = 1; - // The following data is written by the timer ADC sample trigger into each of the SPI TXFIFOs. Note // that because the SPI MOSI line is not connected, this data is dont-care. Data in AXI SRAM is not // initialized on boot, so the contents are random. @@ -32,16 +29,16 @@ static mut SPI_START: [u16; 1] = [0x00]; // processed). Note that the contents of AXI SRAM is uninitialized, so the buffer contents on // startup are undefined. #[link_section = ".axisram.buffers"] -static mut ADC0_BUF0: [u16; INPUT_BUFFER_SIZE] = [0; INPUT_BUFFER_SIZE]; +static mut ADC0_BUF0: [u16; SAMPLE_BUFFER_SIZE] = [0; SAMPLE_BUFFER_SIZE]; #[link_section = ".axisram.buffers"] -static mut ADC0_BUF1: [u16; INPUT_BUFFER_SIZE] = [0; INPUT_BUFFER_SIZE]; +static mut ADC0_BUF1: [u16; SAMPLE_BUFFER_SIZE] = [0; SAMPLE_BUFFER_SIZE]; #[link_section = ".axisram.buffers"] -static mut ADC1_BUF0: [u16; INPUT_BUFFER_SIZE] = [0; INPUT_BUFFER_SIZE]; +static mut ADC1_BUF0: [u16; SAMPLE_BUFFER_SIZE] = [0; SAMPLE_BUFFER_SIZE]; #[link_section = ".axisram.buffers"] -static mut ADC1_BUF1: [u16; INPUT_BUFFER_SIZE] = [0; INPUT_BUFFER_SIZE]; +static mut ADC1_BUF1: [u16; SAMPLE_BUFFER_SIZE] = [0; SAMPLE_BUFFER_SIZE]; /// SPI2 is used as a ZST (zero-sized type) for indicating a DMA transfer into the SPI2 TX FIFO /// whenever the tim2 update dma request occurs. @@ -110,7 +107,7 @@ impl AdcInputs { /// are returned - one for each ADC sample stream. pub fn transfer_complete_handler( &mut self, - ) -> (&[u16; INPUT_BUFFER_SIZE], &[u16; INPUT_BUFFER_SIZE]) { + ) -> (&[u16; SAMPLE_BUFFER_SIZE], &[u16; SAMPLE_BUFFER_SIZE]) { let adc0_buffer = self.adc0.transfer_complete_handler(); let adc1_buffer = self.adc1.transfer_complete_handler(); (adc0_buffer, adc1_buffer) @@ -119,12 +116,12 @@ impl AdcInputs { /// Represents data associated with ADC0. pub struct Adc0Input { - next_buffer: Option<&'static mut [u16; INPUT_BUFFER_SIZE]>, + next_buffer: Option<&'static mut [u16; SAMPLE_BUFFER_SIZE]>, transfer: Transfer< hal::dma::dma::Stream1, hal::spi::Spi, PeripheralToMemory, - &'static mut [u16; INPUT_BUFFER_SIZE], + &'static mut [u16; SAMPLE_BUFFER_SIZE], >, _trigger_transfer: Transfer< hal::dma::dma::Stream0, @@ -223,7 +220,7 @@ impl Adc0Input { /// /// # Returns /// A reference to the underlying buffer that has been filled with ADC samples. - pub fn transfer_complete_handler(&mut self) -> &[u16; INPUT_BUFFER_SIZE] { + pub fn transfer_complete_handler(&mut self) -> &[u16; SAMPLE_BUFFER_SIZE] { let next_buffer = self.next_buffer.take().unwrap(); // Wait for the transfer to fully complete before continuing. @@ -241,12 +238,12 @@ impl Adc0Input { /// Represents the data input stream from ADC1 pub struct Adc1Input { - next_buffer: Option<&'static mut [u16; INPUT_BUFFER_SIZE]>, + next_buffer: Option<&'static mut [u16; SAMPLE_BUFFER_SIZE]>, transfer: Transfer< hal::dma::dma::Stream3, hal::spi::Spi, PeripheralToMemory, - &'static mut [u16; INPUT_BUFFER_SIZE], + &'static mut [u16; SAMPLE_BUFFER_SIZE], >, _trigger_transfer: Transfer< hal::dma::dma::Stream2, @@ -345,7 +342,7 @@ impl Adc1Input { /// /// # Returns /// A reference to the underlying buffer that has been filled with ADC samples. - pub fn transfer_complete_handler(&mut self) -> &[u16; INPUT_BUFFER_SIZE] { + pub fn transfer_complete_handler(&mut self) -> &[u16; SAMPLE_BUFFER_SIZE] { let next_buffer = self.next_buffer.take().unwrap(); // Wait for the transfer to fully complete before continuing. diff --git a/src/dac.rs b/src/dac.rs index 8829385..8057a5a 100644 --- a/src/dac.rs +++ b/src/dac.rs @@ -1,114 +1,279 @@ -///! Stabilizer DAC output control +///! Stabilizer DAC management interface ///! -///! Stabilizer output DACs do not currently rely on DMA requests for generating output. -///! Instead, the DACs utilize an internal queue for storing output codes. A timer then periodically -///! generates an interrupt which triggers an update of the DACs via a write over SPI. -use super::hal; -use heapless::consts; +///! The Stabilizer DAC utilize a DMA channel to generate output updates. A timer channel is +///! configured to generate a DMA write into the SPI TXFIFO, which initiates a SPI transfer and +///! results in DAC update for both channels. +use super::{ + hal, sampling_timer, DMAReq, DmaConfig, MemoryToPeripheral, TargetAddress, + Transfer, SAMPLE_BUFFER_SIZE, +}; -/// Controller structure for managing the DAC outputs. +// The following global buffers are used for the DAC code DMA transfers. Two buffers are used for +// each transfer in a ping-pong buffer configuration (one is being prepared while the other is being +// processed). Note that the contents of AXI SRAM is uninitialized, so the buffer contents on +// startup are undefined. +#[link_section = ".axisram.buffers"] +static mut DAC0_BUF0: [u16; SAMPLE_BUFFER_SIZE] = [0; SAMPLE_BUFFER_SIZE]; + +#[link_section = ".axisram.buffers"] +static mut DAC0_BUF1: [u16; SAMPLE_BUFFER_SIZE] = [0; SAMPLE_BUFFER_SIZE]; + +#[link_section = ".axisram.buffers"] +static mut DAC1_BUF0: [u16; SAMPLE_BUFFER_SIZE] = [0; SAMPLE_BUFFER_SIZE]; + +#[link_section = ".axisram.buffers"] +static mut DAC1_BUF1: [u16; SAMPLE_BUFFER_SIZE] = [0; SAMPLE_BUFFER_SIZE]; + +/// SPI4 is used as a ZST (zero-sized type) for indicating a DMA transfer into the SPI4 TX FIFO +struct SPI4 {} +impl SPI4 { + pub fn new() -> Self { + Self {} + } +} + +unsafe impl TargetAddress for SPI4 { + /// SPI2 is configured to operate using 16-bit transfer words. + type MemSize = u16; + + /// SPI4 DMA requests are generated whenever TIM2 CH3 comparison occurs. + const REQUEST_LINE: Option = Some(DMAReq::TIM2_CH3 as u8); + + /// Whenever the DMA request occurs, it should write into SPI4's TX FIFO. + fn address(&self) -> u32 { + let regs = unsafe { &*hal::stm32::SPI4::ptr() }; + ®s.txdr as *const _ as u32 + } +} + +/// SPI5 is used as a ZST (zero-sized type) for indicating a DMA transfer into the SPI5 TX FIFO +struct SPI5 {} +impl SPI5 { + pub fn new() -> Self { + Self {} + } +} + +unsafe impl TargetAddress for SPI5 { + /// SPI5 is configured to operate using 16-bit transfer words. + type MemSize = u16; + + /// SPI5 DMA requests are generated whenever TIM2 CH4 comparison occurs. + const REQUEST_LINE: Option = Some(DMAReq::TIM2_CH4 as u8); + + /// Whenever the DMA request occurs, it should write into SPI5's TX FIFO + fn address(&self) -> u32 { + let regs = unsafe { &*hal::stm32::SPI5::ptr() }; + ®s.txdr as *const _ as u32 + } +} + +/// Represents both DAC output channels. pub struct DacOutputs { - dac0_spi: hal::spi::Spi, - dac1_spi: hal::spi::Spi, - timer: hal::timer::Timer, - - // The queue is provided a default length of 32 updates, but this queue can be updated by the - // end user to be larger if necessary. - outputs: heapless::spsc::Queue<(u16, u16), consts::U32>, + dac0: Dac0Output, + dac1: Dac1Output, } impl DacOutputs { - /// Construct a new set of DAC output controls - /// - /// # Args - /// * `dac0_spi` - The SPI interface to the DAC0 output. - /// * `dac1_spi` - The SPI interface to the DAC1 output. - /// * `timer` - The timer used to generate periodic events for updating the DACs. - pub fn new( - mut dac0_spi: hal::spi::Spi, - mut dac1_spi: hal::spi::Spi, - mut timer: hal::timer::Timer, - ) -> Self { - // Start the DAC SPI interfaces in infinite transaction mode. CS is configured in - // auto-suspend mode. - dac0_spi.inner().cr1.modify(|_, w| w.cstart().started()); - dac1_spi.inner().cr1.modify(|_, w| w.cstart().started()); - - dac0_spi.listen(hal::spi::Event::Error); - dac1_spi.listen(hal::spi::Event::Error); - - // Stop the timer and begin listening for timeouts. Timeouts will be used as a means to - // generate new DAC outputs. - timer.pause(); - timer.reset_counter(); - timer.clear_irq(); - timer.listen(hal::timer::Event::TimeOut); - - Self { - dac0_spi, - dac1_spi, - outputs: heapless::spsc::Queue::new(), - timer, - } + /// Construct the DAC outputs. + pub fn new(dac0: Dac0Output, dac1: Dac1Output) -> Self { + Self { dac0, dac1 } } - /// Push a set of new DAC output codes to the internal queue. - /// - /// # Note - /// The earlier DAC output codes will be generated within 1 update cycle of the codes. This is a - /// fixed latency currently. - /// - /// This function will panic if too many codes are written. + /// Enqueue the next DAC output codes for transmission. /// /// # Args - /// * `dac0_value` - The value to enqueue for a DAC0 update. - /// * `dac1_value` - The value to enqueue for a DAC1 update. - pub fn push(&mut self, dac0_value: u16, dac1_value: u16) { - self.outputs.enqueue((dac0_value, dac1_value)).unwrap(); - self.timer.resume(); - } - - /// Update the DAC codes with the next set of values in the internal queue. - /// - /// # Note - /// This is intended to be called from the TIM3 update ISR. - /// - /// If the last value in the queue is used, the timer is stopped. - pub fn update(&mut self) { - self.timer.clear_irq(); - match self.outputs.dequeue() { - Some((dac0, dac1)) => self.write(dac0, dac1), - None => { - self.timer.pause(); - self.timer.reset_counter(); - self.timer.clear_irq(); - } - }; - } - - /// Write immediate values to the DAC outputs. - /// - /// # Note - /// The DACs will be updated as soon as the SPI transfer completes, which will be nominally - /// 320nS after this function call. - /// - /// # Args - /// * `dac0_value` - The output code to write to DAC0. - /// * `dac1_value` - The output code to write to DAC1. - pub fn write(&mut self, dac0_value: u16, dac1_value: u16) { - // In order to optimize throughput and minimize latency, the DAC codes are written directly - // into the SPI TX FIFO. No error checking is conducted. Errors are handled via interrupts - // instead. - unsafe { - core::ptr::write_volatile( - &self.dac0_spi.inner().txdr as *const _ as *mut u16, - dac0_value, - ); - - core::ptr::write_volatile( - &self.dac1_spi.inner().txdr as *const _ as *mut u16, - dac1_value, - ); - } + /// * `dac0_codes` - The output codes for DAC0 to enqueue. + /// * `dac1_codes` - The output codes for DAC1 to enqueue. + pub fn next_data( + &mut self, + dac0_codes: &[u16; SAMPLE_BUFFER_SIZE], + dac1_codes: &[u16; SAMPLE_BUFFER_SIZE], + ) { + self.dac0.next_data(dac0_codes); + self.dac1.next_data(dac1_codes); + } +} + +/// Represents data associated with DAC0. +pub struct Dac0Output { + next_buffer: Option<&'static mut [u16; SAMPLE_BUFFER_SIZE]>, + _spi: hal::spi::Spi, + transfer: Transfer< + hal::dma::dma::Stream4, + SPI4, + MemoryToPeripheral, + &'static mut [u16; SAMPLE_BUFFER_SIZE], + >, + first_transfer: bool, +} + +impl Dac0Output { + /// Construct the DAC0 output channel. + /// + /// # Args + /// * `spi` - The SPI interface used to communicate with the ADC. + /// * `stream` - The DMA stream used to write DAC codes over SPI. + /// * `trigger_channel` - The sampling timer output compare channel for update triggers. + pub fn new( + spi: hal::spi::Spi, + stream: hal::dma::dma::Stream4, + trigger_channel: sampling_timer::Timer2Channel3, + ) -> Self { + // Generate DMA events when an output compare of the timer hitting zero (timer roll over) + // occurs. + trigger_channel.listen_dma(); + trigger_channel.to_output_compare(0); + + // The stream constantly writes to the TX FIFO to write new update codes. + let trigger_config = DmaConfig::default() + .memory_increment(true) + .peripheral_increment(false); + + // Construct the trigger stream to write from memory to the peripheral. + let transfer: Transfer<_, _, MemoryToPeripheral, _> = Transfer::init( + stream, + SPI4::new(), + unsafe { &mut DAC0_BUF0 }, + None, + trigger_config, + ); + + // Listen for any potential SPI error signals, which may indicate that we are not generating + // update codes. + let mut spi = spi.disable(); + spi.listen(hal::spi::Event::Error); + + // Allow the SPI FIFOs to operate using only DMA data channels. + spi.enable_dma_tx(); + + // Enable SPI and start it in infinite transaction mode. + spi.inner().cr1.modify(|_, w| w.spe().set_bit()); + spi.inner().cr1.modify(|_, w| w.cstart().started()); + + Self { + transfer, + next_buffer: unsafe { Some(&mut DAC0_BUF1) }, + _spi: spi, + first_transfer: true, + } + } + + /// Schedule the next set of DAC update codes. + /// + /// # Args + /// * `data` - The next samples to enqueue for transmission. + pub fn next_data(&mut self, data: &[u16; SAMPLE_BUFFER_SIZE]) { + let next_buffer = self.next_buffer.take().unwrap(); + + // Copy data into the next buffer + next_buffer.copy_from_slice(data); + + // If the last transfer was not complete, we didn't write all our previous DAC codes. + // Wait for all the DAC codes to get written as well. + if self.first_transfer { + self.first_transfer = false + } else { + while self.transfer.get_transfer_complete_flag() == false {} + } + + // Start the next transfer. + self.transfer.clear_interrupts(); + let (prev_buffer, _) = + self.transfer.next_transfer(next_buffer).unwrap(); + + self.next_buffer.replace(prev_buffer); + } +} + +/// Represents the data output stream from DAC1. +pub struct Dac1Output { + next_buffer: Option<&'static mut [u16; SAMPLE_BUFFER_SIZE]>, + _spi: hal::spi::Spi, + transfer: Transfer< + hal::dma::dma::Stream5, + SPI5, + MemoryToPeripheral, + &'static mut [u16; SAMPLE_BUFFER_SIZE], + >, + first_transfer: bool, +} + +impl Dac1Output { + /// Construct a new DAC1 output data stream. + /// + /// # Args + /// * `spi` - The SPI interface connected to DAC1. + /// * `stream` - The DMA stream used to write DAC codes the SPI TX FIFO. + /// * `trigger_channel` - The timer channel used to generate DMA requests for DAC updates. + pub fn new( + spi: hal::spi::Spi, + stream: hal::dma::dma::Stream5, + trigger_channel: sampling_timer::Timer2Channel4, + ) -> Self { + // Generate DMA events when an output compare of the timer hitting zero (timer roll over) + // occurs. + trigger_channel.listen_dma(); + trigger_channel.to_output_compare(0); + + // The trigger stream constantly writes to the TX FIFO to generate DAC updates. + let trigger_config = DmaConfig::default() + .memory_increment(true) + .peripheral_increment(false) + .circular_buffer(true); + + // Construct the stream to write from memory to the peripheral. + let transfer: Transfer<_, _, MemoryToPeripheral, _> = Transfer::init( + stream, + SPI5::new(), + unsafe { &mut DAC1_BUF0 }, + None, + trigger_config, + ); + + // Listen for any SPI errors, as this may indicate that we are not generating updates on the + // DAC. + let mut spi = spi.disable(); + spi.listen(hal::spi::Event::Error); + + // Allow the SPI FIFOs to operate using only DMA data channels. + spi.enable_dma_tx(); + + // Enable SPI and start it in infinite transaction mode. + spi.inner().cr1.modify(|_, w| w.spe().set_bit()); + spi.inner().cr1.modify(|_, w| w.cstart().started()); + + Self { + next_buffer: unsafe { Some(&mut DAC1_BUF1) }, + transfer, + _spi: spi, + first_transfer: true, + } + } + + /// Enqueue the next buffer for transmission to the DAC. + /// + /// # Args + /// * `data` - The next data to write to the DAC. + pub fn next_data(&mut self, data: &[u16; SAMPLE_BUFFER_SIZE]) { + let next_buffer = self.next_buffer.take().unwrap(); + + // Copy data into the next buffer + next_buffer.copy_from_slice(data); + + // If the last transfer was not complete, we didn't write all our previous DAC codes. + // Wait for all the DAC codes to get written as well. + if self.first_transfer { + self.first_transfer = false + } else { + while self.transfer.get_transfer_complete_flag() == false {} + } + + // Start the next transfer. + self.transfer.clear_interrupts(); + let (prev_buffer, _) = + self.transfer.next_transfer(next_buffer).unwrap(); + + self.next_buffer.replace(prev_buffer); } } diff --git a/src/main.rs b/src/main.rs index 59b19fc..6060d4f 100644 --- a/src/main.rs +++ b/src/main.rs @@ -51,8 +51,12 @@ use smoltcp::wire::Ipv4Address; use heapless::{consts::*, String}; +// The desired sampling frequency of the ADCs. const SAMPLE_FREQUENCY_KHZ: u32 = 500; +// The desired ADC sample processing buffer size. +const SAMPLE_BUFFER_SIZE: usize = 1; + #[link_section = ".sram3.eth"] static mut DES_RING: ethernet::DesRing = ethernet::DesRing::new(); @@ -66,7 +70,7 @@ mod sampling_timer; mod server; use adc::{Adc0Input, Adc1Input, AdcInputs}; -use dac::DacOutputs; +use dac::{Dac0Output, Dac1Output, DacOutputs}; #[cfg(not(feature = "semihosting"))] fn init_log() {} @@ -426,13 +430,17 @@ const APP: () = { ) }; - let timer = dp.TIM3.timer( - SAMPLE_FREQUENCY_KHZ.khz(), - ccdr.peripheral.TIM3, - &ccdr.clocks, + let dac0 = Dac0Output::new( + dac0_spi, + dma_streams.4, + sampling_timer_channels.ch3, ); - - DacOutputs::new(dac0_spi, dac1_spi, timer) + let dac1 = Dac1Output::new( + dac1_spi, + dma_streams.5, + sampling_timer_channels.ch4, + ); + DacOutputs::new(dac0, dac1) }; let mut fp_led_0 = gpiod.pd5.into_push_pull_output(); @@ -735,35 +743,33 @@ const APP: () = { } } - #[task(binds = TIM3, resources=[dacs], priority = 3)] - fn dac_update(c: dac_update::Context) { - c.resources.dacs.update(); - } - #[task(binds=DMA1_STR3, resources=[adcs, dacs, iir_state, iir_ch], priority=2)] - fn adc_update(mut c: adc_update::Context) { + fn adc_update(c: adc_update::Context) { let (adc0_samples, adc1_samples) = c.resources.adcs.transfer_complete_handler(); - for (adc0, adc1) in adc0_samples.iter().zip(adc1_samples.iter()) { - let result_adc0 = { + let mut dac0: [u16; SAMPLE_BUFFER_SIZE] = [0; SAMPLE_BUFFER_SIZE]; + let mut dac1: [u16; SAMPLE_BUFFER_SIZE] = [0; SAMPLE_BUFFER_SIZE]; + + for (i, (adc0, adc1)) in + adc0_samples.iter().zip(adc1_samples.iter()).enumerate() + { + dac0[i] = { let x0 = f32::from(*adc0 as i16); let y0 = c.resources.iir_ch[0] .update(&mut c.resources.iir_state[0], x0); y0 as i16 as u16 ^ 0x8000 }; - let result_adc1 = { + dac1[i] = { let x1 = f32::from(*adc1 as i16); let y1 = c.resources.iir_ch[1] .update(&mut c.resources.iir_state[1], x1); y1 as i16 as u16 ^ 0x8000 }; - - c.resources - .dacs - .lock(|dacs| dacs.push(result_adc0, result_adc1)); } + + c.resources.dacs.next_data(&dac0, &dac1); } #[idle(resources=[net_interface, pounder, mac_addr, eth_mac, iir_state, iir_ch, afe0, afe1])] diff --git a/src/sampling_timer.rs b/src/sampling_timer.rs index b412b75..7b3b557 100644 --- a/src/sampling_timer.rs +++ b/src/sampling_timer.rs @@ -103,5 +103,45 @@ impl Timer2Channel2 { /// Representation of CH3 of TIM2. pub struct Timer2Channel3 {} +impl Timer2Channel3 { + /// Allow CH4 to generate DMA requests. + pub fn listen_dma(&self) { + let regs = unsafe { &*hal::stm32::TIM2::ptr() }; + regs.dier.modify(|_, w| w.cc3de().set_bit()); + } + + /// Operate CH2 as an output-compare. + /// + /// # Args + /// * `value` - The value to compare the sampling timer's counter against. + pub fn to_output_compare(&self, value: u32) { + let regs = unsafe { &*hal::stm32::TIM2::ptr() }; + assert!(value <= regs.arr.read().bits()); + regs.ccr3.write(|w| w.ccr().bits(value)); + regs.ccmr2_output() + .modify(|_, w| unsafe { w.cc3s().bits(0) }); + } +} + /// Representation of CH4 of TIM2. pub struct Timer2Channel4 {} + +impl Timer2Channel4 { + /// Allow CH4 to generate DMA requests. + pub fn listen_dma(&self) { + let regs = unsafe { &*hal::stm32::TIM2::ptr() }; + regs.dier.modify(|_, w| w.cc4de().set_bit()); + } + + /// Operate CH2 as an output-compare. + /// + /// # Args + /// * `value` - The value to compare the sampling timer's counter against. + pub fn to_output_compare(&self, value: u32) { + let regs = unsafe { &*hal::stm32::TIM2::ptr() }; + assert!(value <= regs.arr.read().bits()); + regs.ccr4.write(|w| w.ccr().bits(value)); + regs.ccmr2_output() + .modify(|_, w| unsafe { w.cc4s().bits(0) }); + } +}