board: enable TIM2 late
This was triggered by moving log_init and adding i2c_init on top of the existing ethernet setup/init after the timer setup and enable. Thanks @cjbe for debugging. Also move the RCC peripheral enable calls out of i2c and eth setup. close #55 supersedes #62
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8e84e61ff3
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19
src/board.rs
19
src/board.rs
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@ -399,8 +399,7 @@ fn tim2_setup(tim2: &pac::TIM2) {
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tim2.dier.write(|w| w.ude().set_bit());
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tim2.dier.write(|w| w.ude().set_bit());
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tim2.egr.write(|w| w.ug().set_bit());
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tim2.egr.write(|w| w.ug().set_bit());
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tim2.cr1.modify(|_, w|
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tim2.cr1.modify(|_, w|
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w.dir().clear_bit() // up
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w.dir().clear_bit()); // up
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.cen().set_bit()); // enable
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}
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}
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fn dma1_setup(dma1: &pac::DMA1, dmamux1: &pac::DMAMUX1, ma: usize, pa0: usize, pa1: usize) {
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fn dma1_setup(dma1: &pac::DMA1, dmamux1: &pac::DMAMUX1, ma: usize, pa0: usize, pa1: usize) {
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@ -524,9 +523,19 @@ pub fn init() {
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tim2_setup(&dp.TIM2);
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tim2_setup(&dp.TIM2);
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let i2c2 = dp.I2C2;
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rcc.apb1lenr.modify(|_,w| w.i2c2en().set_bit());
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i2c::setup(&rcc, &i2c2);
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i2c::setup(&dp.I2C2);
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eth::setup(&rcc, &dp.SYSCFG);
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rcc.apb4enr.modify(|_, w| w.syscfgen().set_bit());
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rcc.ahb1enr.modify(|_, w| {
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w.eth1macen().set_bit()
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.eth1txen().set_bit()
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.eth1rxen().set_bit()
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});
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dp.SYSCFG.pmcr.modify(|_, w| unsafe { w.epis().bits(0b100) }); // RMII
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eth::setup_pins(&dp.GPIOA, &dp.GPIOB, &dp.GPIOC, &dp.GPIOG);
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eth::setup_pins(&dp.GPIOA, &dp.GPIOB, &dp.GPIOC, &dp.GPIOG);
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// enable TIM2 this must be late to be able to handle the first ADC SPI
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// interrupt in time
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dp.TIM2.cr1.modify(|_, w| w.cen().set_bit());
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}
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}
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13
src/eth.rs
13
src/eth.rs
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@ -85,19 +85,6 @@ use self::cr_consts::*;
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// 200 MHz AHB clock = eth_hclk
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// 200 MHz AHB clock = eth_hclk
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const CLOCK_RANGE: u8 = ETH_MACMIIAR_CR_HCLK_DIV_102;
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const CLOCK_RANGE: u8 = ETH_MACMIIAR_CR_HCLK_DIV_102;
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pub fn setup(rcc: &pac::RCC, syscfg: &pac::SYSCFG) {
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rcc.apb4enr.modify(|_, w| w.syscfgen().set_bit());
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rcc.ahb1enr.modify(|_, w| {
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w.eth1macen().set_bit()
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.eth1txen().set_bit()
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.eth1rxen().set_bit()
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});
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syscfg.pmcr.modify(|_, w| unsafe { w.epis().bits(0b100) }); // RMII
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//rcc.ahb1rstr.modify(|_, w| w.eth1macrst().set_bit());
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//rcc.ahb1rstr.modify(|_, w| w.eth1macrst().clear_bit());
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}
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pub fn setup_pins(gpioa: &pac::GPIOA, gpiob: &pac::GPIOB,
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pub fn setup_pins(gpioa: &pac::GPIOA, gpiob: &pac::GPIOB,
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gpioc: &pac::GPIOC, gpiog: &pac::GPIOG) {
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gpioc: &pac::GPIOC, gpiog: &pac::GPIOG) {
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// PA1 RMII_REF_CLK
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// PA1 RMII_REF_CLK
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@ -21,11 +21,7 @@ pub enum Error {
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const N_RETRY: usize = 100; // ~ 10ms @ 100 kHz bus clock
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const N_RETRY: usize = 100; // ~ 10ms @ 100 kHz bus clock
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pub fn setup(rcc: &pac::RCC, i2c: &pac::I2C2) {
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pub fn setup(i2c: &pac::I2C2) {
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rcc.apb1lenr.modify(|_,w|
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w.i2c2en().set_bit()
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);
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// Disable the peripheral before setting timings
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// Disable the peripheral before setting timings
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i2c.cr1.modify(|_, w| w.pe().clear_bit());
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i2c.cr1.modify(|_, w| w.pe().clear_bit());
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