2021-01-20 21:19:28 +08:00
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#![deny(warnings)]
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#![no_std]
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#![no_main]
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2021-02-23 23:57:09 +08:00
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use generic_array::typenum::U4;
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2021-03-02 02:48:45 +08:00
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2021-03-03 22:01:28 +08:00
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use miniconf::{minimq, Miniconf, MqttInterface};
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2021-03-02 02:48:45 +08:00
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use serde::Deserialize;
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use dsp::{Accu, Complex, ComplexExt, Lockin, RPLL};
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use stabilizer::hardware::{
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design_parameters, setup, Adc0Input, Adc1Input, AfeGain, CycleCounter,
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Dac0Output, Dac1Output, InputStamper, NetworkStack, AFE0, AFE1,
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2021-01-20 21:29:29 +08:00
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};
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2021-03-02 02:48:45 +08:00
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2021-03-03 00:29:20 +08:00
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#[derive(Copy, Clone, Debug, Deserialize, Miniconf)]
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2021-03-02 02:48:45 +08:00
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enum Conf {
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PowerPhase,
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FrequencyDiscriminator,
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Quadrature,
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}
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2021-03-03 00:29:20 +08:00
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#[derive(Copy, Clone, Debug, Deserialize, Miniconf)]
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2021-03-02 02:48:45 +08:00
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pub struct Settings {
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afe: [AfeGain; 2],
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pll_tc: [u8; 2],
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lockin_tc: u8,
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lockin_harmonic: i32,
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lockin_phase: i32,
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2021-03-02 18:46:19 +08:00
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output_conf: [Conf; 2],
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2021-03-02 02:48:45 +08:00
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}
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impl Default for Settings {
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fn default() -> Self {
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Self {
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2021-03-02 18:46:19 +08:00
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afe: [AfeGain::G1; 2],
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2021-03-02 02:48:45 +08:00
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pll_tc: [21, 21], // frequency and phase settling time (log2 counter cycles)
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lockin_tc: 6, // lockin lowpass time constant
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lockin_harmonic: -1, // Harmonic index of the LO: -1 to _de_modulate the fundamental (complex conjugate)
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lockin_phase: 0, // Demodulation LO phase offset
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2021-03-02 18:46:19 +08:00
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output_conf: [Conf::Quadrature; 2],
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2021-03-02 02:48:45 +08:00
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}
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}
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}
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2021-01-20 21:29:29 +08:00
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2021-01-20 21:19:28 +08:00
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#[rtic::app(device = stm32h7xx_hal::stm32, peripherals = true, monotonic = rtic::cyccnt::CYCCNT)]
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const APP: () = {
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struct Resources {
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afes: (AFE0, AFE1),
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adcs: (Adc0Input, Adc1Input),
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dacs: (Dac0Output, Dac1Output),
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2021-03-02 02:48:45 +08:00
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clock: CycleCounter,
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mqtt_interface:
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MqttInterface<Settings, NetworkStack, minimq::consts::U256>,
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settings: Settings,
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2021-01-20 21:29:29 +08:00
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timestamper: InputStamper,
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2021-01-25 18:45:55 +08:00
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pll: RPLL,
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2021-02-23 23:46:16 +08:00
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lockin: Lockin<U4>,
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2021-01-20 21:19:28 +08:00
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}
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2021-03-02 02:48:45 +08:00
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#[init(spawn=[settings_update])]
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2021-01-20 21:19:28 +08:00
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fn init(c: init::Context) -> init::LateResources {
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// Configure the microcontroller
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2021-03-02 02:48:45 +08:00
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let (mut stabilizer, _pounder) = setup(c.core, c.device);
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let mqtt_interface = {
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2021-03-03 22:01:28 +08:00
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let mqtt_client = minimq::MqttClient::new(
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design_parameters::MQTT_BROKER.into(),
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"",
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stabilizer.net.stack,
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)
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.unwrap();
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2021-03-02 02:48:45 +08:00
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2021-03-03 02:04:39 +08:00
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MqttInterface::new(
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mqtt_client,
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"dt/sinara/lockin",
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Settings::default(),
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)
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.unwrap()
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};
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let settings = Settings::default();
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2021-01-20 21:19:28 +08:00
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2021-02-04 19:48:25 +08:00
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let pll = RPLL::new(
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design_parameters::ADC_SAMPLE_TICKS_LOG2
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+ design_parameters::SAMPLE_BUFFER_SIZE_LOG2,
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2021-01-21 21:55:33 +08:00
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);
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2021-01-20 21:29:29 +08:00
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2021-03-02 02:48:45 +08:00
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// Spawn a settings update for default settings.
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c.spawn.settings_update().unwrap();
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2021-01-20 21:19:28 +08:00
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// Enable ADC/DAC events
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stabilizer.adcs.0.start();
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stabilizer.adcs.1.start();
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stabilizer.dacs.0.start();
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stabilizer.dacs.1.start();
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2021-01-21 21:55:33 +08:00
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// Start recording digital input timestamps.
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stabilizer.timestamp_timer.start();
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2021-01-21 23:12:59 +08:00
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// Start sampling ADCs.
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stabilizer.adc_dac_timer.start();
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2021-02-03 20:03:17 +08:00
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// Enable the timestamper.
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stabilizer.timestamper.start();
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2021-01-20 21:19:28 +08:00
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init::LateResources {
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afes: stabilizer.afes,
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adcs: stabilizer.adcs,
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dacs: stabilizer.dacs,
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2021-01-20 21:29:29 +08:00
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timestamper: stabilizer.timestamper,
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2021-03-02 02:48:45 +08:00
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clock: stabilizer.cycle_counter,
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mqtt_interface,
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settings,
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2021-02-18 00:22:43 +08:00
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2021-01-21 21:55:33 +08:00
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pll,
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2021-02-15 00:55:01 +08:00
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lockin: Lockin::default(),
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2021-01-20 21:19:28 +08:00
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}
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}
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2021-02-02 22:50:31 +08:00
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/// Main DSP processing routine.
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///
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2021-02-02 22:50:31 +08:00
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/// See `dual-iir` for general notes on processing time and timing.
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2021-01-20 21:19:28 +08:00
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///
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2021-02-02 22:50:31 +08:00
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/// This is an implementation of a externally (DI0) referenced PLL lockin on the ADC0 signal.
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/// It outputs either I/Q or power/phase on DAC0/DAC1. Data is normalized to full scale.
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/// PLL bandwidth, filter bandwidth, slope, and x/y or power/phase post-filters are available.
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2021-03-02 02:48:45 +08:00
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#[task(binds=DMA1_STR4, resources=[adcs, dacs, lockin, timestamper, pll, settings], priority=2)]
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fn process(c: process::Context) {
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let adc_samples = [
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c.resources.adcs.0.acquire_buffer(),
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c.resources.adcs.1.acquire_buffer(),
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];
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let dac_samples = [
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c.resources.dacs.0.acquire_buffer(),
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c.resources.dacs.1.acquire_buffer(),
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];
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2021-01-21 21:55:33 +08:00
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let lockin = c.resources.lockin;
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let settings = c.resources.settings;
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2021-01-20 21:19:28 +08:00
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2021-03-02 18:46:19 +08:00
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let timestamp =
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c.resources.timestamper.latest_timestamp().unwrap_or(None); // Ignore data from timer capture overflows.
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let (pll_phase, pll_frequency) = c.resources.pll.update(
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2021-03-02 18:46:19 +08:00
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timestamp.map(|t| t as i32),
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settings.pll_tc[0],
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settings.pll_tc[1],
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2021-01-25 18:45:55 +08:00
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);
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2021-01-20 21:19:28 +08:00
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2021-02-02 01:14:09 +08:00
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let sample_frequency = ((pll_frequency
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2021-02-04 19:48:25 +08:00
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>> design_parameters::SAMPLE_BUFFER_SIZE_LOG2)
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as i32)
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2021-03-02 02:48:45 +08:00
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.wrapping_mul(settings.lockin_harmonic);
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let sample_phase = settings
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.lockin_phase
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.wrapping_add(pll_phase.wrapping_mul(settings.lockin_harmonic));
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2021-01-20 21:19:28 +08:00
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2021-02-18 21:06:01 +08:00
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let output: Complex<i32> = adc_samples[0]
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2021-02-01 20:42:21 +08:00
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.iter()
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2021-02-18 21:06:01 +08:00
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// Zip in the LO phase.
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2021-02-01 20:42:21 +08:00
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.zip(Accu::new(sample_phase, sample_frequency))
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2021-02-18 21:06:01 +08:00
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// Convert to signed, MSB align the ADC sample, update the Lockin (demodulate, filter)
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2021-02-01 20:42:21 +08:00
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.map(|(&sample, phase)| {
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2021-02-19 01:50:31 +08:00
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let s = (sample as i16 as i32) << 16;
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2021-03-02 02:48:45 +08:00
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lockin.update(s, phase, settings.lockin_tc)
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2021-02-01 20:42:21 +08:00
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})
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2021-02-18 21:06:01 +08:00
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// Decimate
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2021-02-01 20:42:21 +08:00
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.last()
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2021-02-19 01:50:31 +08:00
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.unwrap()
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* 2; // Full scale assuming the 2f component is gone.
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2021-02-02 01:14:09 +08:00
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2021-03-02 18:46:19 +08:00
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let output = [
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match settings.output_conf[0] {
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Conf::PowerPhase => output.abs_sqr() as _,
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Conf::FrequencyDiscriminator => (output.log2() << 24) as _,
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Conf::Quadrature => output.re,
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},
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match settings.output_conf[1] {
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Conf::PowerPhase => output.arg(),
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Conf::FrequencyDiscriminator => pll_frequency as _,
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Conf::Quadrature => output.im,
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},
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];
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2021-02-02 01:14:09 +08:00
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// Convert to DAC data.
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for i in 0..dac_samples[0].len() {
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2021-02-06 01:59:22 +08:00
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dac_samples[0][i] = (output[0] >> 16) as u16 ^ 0x8000;
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dac_samples[1][i] = (output[1] >> 16) as u16 ^ 0x8000;
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2021-01-20 21:19:28 +08:00
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}
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}
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2021-03-02 02:48:45 +08:00
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#[idle(resources=[mqtt_interface, clock], spawn=[settings_update])]
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fn idle(mut c: idle::Context) -> ! {
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let clock = c.resources.clock;
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2021-01-20 21:19:28 +08:00
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loop {
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2021-03-02 02:48:45 +08:00
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let sleep = c.resources.mqtt_interface.lock(|interface| {
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2021-03-15 18:41:13 +08:00
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match interface.network_stack().poll(clock.current_ms()) {
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Ok(updated) => !updated,
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Err(err) => {
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log::info!("Network error: {:?}", err);
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2021-03-17 21:56:31 +08:00
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false
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2021-03-15 18:41:13 +08:00
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}
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}
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2021-03-02 02:48:45 +08:00
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});
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2021-03-17 21:47:14 +08:00
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match c
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.resources
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.mqtt_interface
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2021-03-17 21:47:14 +08:00
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.lock(|interface| interface.update())
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{
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2021-03-17 21:47:14 +08:00
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Ok(update) => {
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if update {
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c.spawn.settings_update().unwrap();
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} else if sleep {
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cortex_m::asm::wfi();
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}
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}
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Err(miniconf::MqttError::Network(
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smoltcp_nal::NetworkError::NoIpAddress,
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)) => {}
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Err(error) => log::info!("Unexpected error: {:?}", error),
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}
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2021-01-20 21:19:28 +08:00
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}
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}
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2021-03-02 02:48:45 +08:00
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#[task(priority = 1, resources=[mqtt_interface, settings, afes])]
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fn settings_update(mut c: settings_update::Context) {
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let settings = &c.resources.mqtt_interface.settings;
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c.resources.afes.0.set_gain(settings.afe[0]);
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c.resources.afes.1.set_gain(settings.afe[1]);
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c.resources.settings.lock(|current| *current = *settings);
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}
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2021-01-20 21:19:28 +08:00
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#[task(binds = ETH, priority = 1)]
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fn eth(_: eth::Context) {
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2021-02-23 23:46:16 +08:00
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unsafe { stm32h7xx_hal::ethernet::interrupt_handler() }
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2021-01-20 21:19:28 +08:00
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}
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#[task(binds = SPI2, priority = 3)]
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fn spi2(_: spi2::Context) {
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panic!("ADC0 input overrun");
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}
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#[task(binds = SPI3, priority = 3)]
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fn spi3(_: spi3::Context) {
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2021-02-23 23:57:09 +08:00
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panic!("ADC1 input overrun");
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2021-01-20 21:19:28 +08:00
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}
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#[task(binds = SPI4, priority = 3)]
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fn spi4(_: spi4::Context) {
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panic!("DAC0 output error");
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}
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#[task(binds = SPI5, priority = 3)]
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fn spi5(_: spi5::Context) {
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panic!("DAC1 output error");
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}
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extern "C" {
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// hw interrupt handlers for RTIC to use for scheduling tasks
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// one per priority
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fn DCMI();
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fn JPEG();
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fn SDMMC();
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}
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};
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