forked from M-Labs/zynq-rs
225 lines
6.9 KiB
Rust
225 lines
6.9 KiB
Rust
use crate::regs::*;
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use crate::slcr;
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mod regs;
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pub struct Eth {
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regs: &'static mut regs::RegisterBlock,
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}
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impl Eth {
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pub fn default() -> Self {
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slcr::RegisterBlock::unlocked(|slcr| {
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// MDIO
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slcr.mio_pin_53.write(
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slcr::MioPin53::zeroed()
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.l3_sel(0b100)
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.io_type(slcr::IoBufferType::Lvcmos18)
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.pullup(true)
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);
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// MDC
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slcr.mio_pin_52.write(
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slcr::MioPin52::zeroed()
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.tri_enable(true)
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.l3_sel(0b100)
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.io_type(slcr::IoBufferType::Lvcmos18)
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.pullup(true)
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);
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// TX_CLK
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slcr.mio_pin_16.write(
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slcr::MioPin16::zeroed()
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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.pullup(true)
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);
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// TX_CTRL
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slcr.mio_pin_21.write(
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slcr::MioPin21::zeroed()
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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.pullup(true)
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);
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// TXD3
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slcr.mio_pin_20.write(
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slcr::MioPin20::zeroed()
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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.pullup(true)
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);
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// TXD2
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slcr.mio_pin_19.write(
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slcr::MioPin19::zeroed()
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.io_type(slcr::IoBufferType::Lvcmos18)
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.pullup(true)
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);
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// TXD1
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slcr.mio_pin_18.write(
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slcr::MioPin18::zeroed()
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.io_type(slcr::IoBufferType::Lvcmos18)
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.pullup(true)
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);
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// TXD0
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slcr.mio_pin_17.write(
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slcr::MioPin17::zeroed()
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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.pullup(true)
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);
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// RX_CLK
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slcr.mio_pin_22.write(
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slcr::MioPin22::zeroed()
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.tri_enable(true)
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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.pullup(true)
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);
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// RX_CTRL
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slcr.mio_pin_27.write(
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slcr::MioPin27::zeroed()
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.tri_enable(true)
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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.pullup(true)
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);
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// RXD3
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slcr.mio_pin_26.write(
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slcr::MioPin26::zeroed()
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.tri_enable(true)
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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.pullup(true)
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);
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// RXD2
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slcr.mio_pin_25.write(
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slcr::MioPin25::zeroed()
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.tri_enable(true)
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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.pullup(true)
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);
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// RXD1
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slcr.mio_pin_24.write(
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slcr::MioPin24::zeroed()
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.tri_enable(true)
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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.pullup(true)
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);
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// RXD0
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slcr.mio_pin_23.write(
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slcr::MioPin23::zeroed()
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.tri_enable(true)
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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.pullup(true)
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);
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});
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Self::gem0()
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}
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pub fn gem0() -> Self {
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slcr::RegisterBlock::unlocked(|slcr| {
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// Enable gem0 ref clock
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slcr.gem0_rclk_ctrl.write(
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slcr::RclkCtrl::zeroed()
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.clkact(true)
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);
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slcr.gem0_clk_ctrl.write(
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slcr::ClkCtrl::zeroed()
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.clkact(true)
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.srcsel(slcr::PllSource::IoPll)
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.divisor(10)
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);
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});
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let regs = regs::RegisterBlock::gem0();
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Eth { regs }.init()
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}
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pub fn gem1() -> Self {
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let regs = regs::RegisterBlock::gem1();
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Eth { regs }.init()
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}
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fn init(self) -> Self {
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// Clear the Network Control register.
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self.regs.net_ctrl.write(regs::NetCtrl::zeroed());
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self.regs.net_ctrl.write(regs::NetCtrl::zeroed().clear_stat_regs(true));
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// Clear the Status registers.
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self.regs.rx_status.write(
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regs::RxStatus::zeroed()
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.buffer_not_avail(true)
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.frame_recd(true)
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.rx_overrun(true)
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.hresp_not_ok(true)
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);
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self.regs.tx_status.write(
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regs::TxStatus::zeroed()
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.used_bit_read(true)
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.collision(true)
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.retry_limit_exceeded(true)
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.tx_go(true)
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.tx_corr_ahb_err(true)
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.tx_complete(true)
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.tx_under_run(true)
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.late_collision(true)
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// not in the manual:
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.hresp_not_ok(true)
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);
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// Disable all interrupts.
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self.regs.intr_dis.write(
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regs::IntrDis::zeroed()
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.mgmt_done(true)
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.rx_complete(true)
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.rx_used_read(true)
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.tx_used_read(true)
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.tx_underrun(true)
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.retry_ex_late_collisn(true)
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.tx_corrupt_ahb_err(true)
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.tx_complete(true)
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.link_chng(true)
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.rx_overrun(true)
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.hresp_not_ok(true)
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.pause_nonzeroq(true)
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.pause_zero(true)
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.pause_tx(true)
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.ex_intr(true)
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.autoneg_complete(true)
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.partner_pg_rx(true)
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.delay_req_rx(true)
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.sync_rx(true)
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.delay_req_tx(true)
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.sync_tx(true)
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.pdelay_req_rx(true)
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.pdelay_resp_rx(true)
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.pdelay_req_tx(true)
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.pdelay_resp_tx(true)
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.tsu_sec_incr(true)
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);
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// Clear the buffer queues.
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self.regs.rx_qbar.write(
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regs::RxQbar::zeroed()
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);
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self.regs.tx_qbar.write(
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regs::TxQbar::zeroed()
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);
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self
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}
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fn configure(&mut self) {
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self.regs.net_cfg.write(
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regs::NetCfg::zeroed()
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.full_duplex(true)
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.gige_en(true)
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.speed(true)
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.no_broadcast(false)
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.multi_hash_en(true)
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// Promiscuous mode
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.copy_all(true)
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.mdc_clk_div(0b111)
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);
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}
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}
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