forked from M-Labs/zynq-rs
497 lines
15 KiB
Rust
497 lines
15 KiB
Rust
use crate::regs::*;
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use crate::slcr;
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use crate::println;
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use crate::clocks::CpuClocks;
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pub mod phy;
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mod regs;
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pub mod rx;
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pub mod tx;
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/// Size of all the buffers
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pub const MTU: usize = 1536;
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/// Maximum MDC clock
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const MAX_MDC: u32 = 2_500_000;
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/// Clock for GbE
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const TX_1000: u32 = 125_000_000;
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pub struct Eth<RX, TX> {
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regs: &'static mut regs::RegisterBlock,
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rx: RX,
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tx: TX,
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}
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impl Eth<(), ()> {
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pub fn default(macaddr: [u8; 6]) -> Self {
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slcr::RegisterBlock::unlocked(|slcr| {
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// Manual example: 0x0000_1280
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// MDIO
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slcr.mio_pin_53.write(
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slcr::MioPin53::zeroed()
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.l3_sel(0b100)
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.io_type(slcr::IoBufferType::Lvcmos18)
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.pullup(true)
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);
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// MDC
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slcr.mio_pin_52.write(
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slcr::MioPin52::zeroed()
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.l3_sel(0b100)
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.io_type(slcr::IoBufferType::Lvcmos18)
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.pullup(true)
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);
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// Manual example: 0x0000_3902
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// TX_CLK
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slcr.mio_pin_16.write(
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slcr::MioPin16::zeroed()
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.l0_sel(true)
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.speed(true)
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.io_type(slcr::IoBufferType::Hstl)
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.pullup(true)
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.disable_rcvr(true)
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);
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// TX_CTRL
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slcr.mio_pin_21.write(
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slcr::MioPin21::zeroed()
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.l0_sel(true)
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.speed(true)
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.io_type(slcr::IoBufferType::Hstl)
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.pullup(true)
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.disable_rcvr(true)
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);
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// TXD3
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slcr.mio_pin_20.write(
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slcr::MioPin20::zeroed()
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.l0_sel(true)
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.speed(true)
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.io_type(slcr::IoBufferType::Hstl)
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.pullup(true)
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.disable_rcvr(true)
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);
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// TXD2
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slcr.mio_pin_19.write(
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slcr::MioPin19::zeroed()
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.l0_sel(true)
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.speed(true)
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.io_type(slcr::IoBufferType::Hstl)
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.pullup(true)
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.disable_rcvr(true)
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);
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// TXD1
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slcr.mio_pin_18.write(
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slcr::MioPin18::zeroed()
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.l0_sel(true)
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.speed(true)
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.io_type(slcr::IoBufferType::Hstl)
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.pullup(true)
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.disable_rcvr(true)
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);
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// TXD0
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slcr.mio_pin_17.write(
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slcr::MioPin17::zeroed()
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.l0_sel(true)
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.speed(true)
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.io_type(slcr::IoBufferType::Hstl)
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.pullup(true)
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.disable_rcvr(true)
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);
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// Manual example: 0x0000_1903
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// RX_CLK
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slcr.mio_pin_22.write(
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slcr::MioPin22::zeroed()
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.tri_enable(true)
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Hstl)
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.pullup(true)
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);
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// RX_CTRL
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slcr.mio_pin_27.write(
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slcr::MioPin27::zeroed()
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.tri_enable(true)
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Hstl)
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.pullup(true)
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);
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// RXD3
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slcr.mio_pin_26.write(
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slcr::MioPin26::zeroed()
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.tri_enable(true)
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Hstl)
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.pullup(true)
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);
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// RXD2
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slcr.mio_pin_25.write(
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slcr::MioPin25::zeroed()
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.tri_enable(true)
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Hstl)
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.pullup(true)
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);
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// RXD1
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slcr.mio_pin_24.write(
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slcr::MioPin24::zeroed()
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.tri_enable(true)
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Hstl)
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.pullup(true)
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);
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// RXD0
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slcr.mio_pin_23.write(
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slcr::MioPin23::zeroed()
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.tri_enable(true)
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Hstl)
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.pullup(true)
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);
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// VREF internal generator
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slcr.gpiob_ctrl.write(
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slcr::GpiobCtrl::zeroed()
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.vref_en(true)
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);
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});
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Self::gem0(macaddr)
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}
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pub fn gem0(macaddr: [u8; 6]) -> Self {
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Self::setup_gem0_clock(TX_1000);
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let regs = regs::RegisterBlock::gem0();
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Self::from_regs(regs, macaddr)
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}
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pub fn gem1(macaddr: [u8; 6]) -> Self {
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Self::setup_gem1_clock(TX_1000);
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let regs = regs::RegisterBlock::gem1();
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Self::from_regs(regs, macaddr)
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}
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fn from_regs(regs: &'static mut regs::RegisterBlock, macaddr: [u8; 6]) -> Self {
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let mut eth = Eth {
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regs,
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rx: (),
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tx: (),
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}.init();
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eth.configure(macaddr);
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eth
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}
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}
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impl<RX, TX> Eth<RX, TX> {
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pub fn setup_gem0_clock(tx_clock: u32) {
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let io_pll = CpuClocks::get().io;
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let d0 = (io_pll / tx_clock).min(63);
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let d1 = (io_pll / tx_clock / d0).min(63);
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.gem0_clk_ctrl.write(
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// 0x0050_0801: 8, 5: 100 Mb/s
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// ...: 8, 1: 1000 Mb/s
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slcr::GemClkCtrl::zeroed()
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.clkact(true)
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.srcsel(slcr::PllSource::IoPll)
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.divisor(d0 as u8)
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.divisor1(d1 as u8)
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);
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// Enable gem0 recv clock
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slcr.gem0_rclk_ctrl.write(
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// 0x0000_0801
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slcr::RclkCtrl::zeroed()
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.clkact(true)
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);
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});
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}
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pub fn setup_gem1_clock(tx_clock: u32) {
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let io_pll = CpuClocks::get().io;
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let d0 = (io_pll / tx_clock).min(63);
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let d1 = (io_pll / tx_clock / d0).min(63);
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.gem1_clk_ctrl.write(
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slcr::GemClkCtrl::zeroed()
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.clkact(true)
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.srcsel(slcr::PllSource::IoPll)
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.divisor(d0 as u8)
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.divisor1(d1 as u8)
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);
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// Enable gem1 recv clock
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slcr.gem1_rclk_ctrl.write(
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// 0x0000_0801
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slcr::RclkCtrl::zeroed()
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.clkact(true)
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);
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});
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}
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fn init(self) -> Self {
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// Clear the Network Control register.
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self.regs.net_ctrl.write(regs::NetCtrl::zeroed());
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self.regs.net_ctrl.write(regs::NetCtrl::zeroed().clear_stat_regs(true));
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// Clear the Status registers.
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self.regs.rx_status.write(
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regs::RxStatus::zeroed()
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.buffer_not_avail(true)
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.frame_recd(true)
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.rx_overrun(true)
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.hresp_not_ok(true)
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);
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self.regs.tx_status.write(
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regs::TxStatus::zeroed()
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.used_bit_read(true)
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.collision(true)
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.retry_limit_exceeded(true)
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.tx_go(true)
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.tx_corr_ahb_err(true)
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.tx_complete(true)
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.tx_under_run(true)
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.late_collision(true)
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// not in the manual:
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.hresp_not_ok(true)
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);
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// Disable all interrupts.
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self.regs.intr_dis.write(
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regs::IntrDis::zeroed()
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.mgmt_done(true)
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.rx_complete(true)
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.rx_used_read(true)
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.tx_used_read(true)
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.tx_underrun(true)
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.retry_ex_late_collisn(true)
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.tx_corrupt_ahb_err(true)
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.tx_complete(true)
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.link_chng(true)
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.rx_overrun(true)
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.hresp_not_ok(true)
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.pause_nonzeroq(true)
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.pause_zero(true)
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.pause_tx(true)
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.ex_intr(true)
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.autoneg_complete(true)
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.partner_pg_rx(true)
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.delay_req_rx(true)
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.sync_rx(true)
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.delay_req_tx(true)
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.sync_tx(true)
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.pdelay_req_rx(true)
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.pdelay_resp_rx(true)
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.pdelay_req_tx(true)
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.pdelay_resp_tx(true)
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.tsu_sec_incr(true)
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);
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// Clear the buffer queues.
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self.regs.rx_qbar.write(
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regs::RxQbar::zeroed()
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);
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self.regs.tx_qbar.write(
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regs::TxQbar::zeroed()
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);
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self
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}
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fn configure(&mut self, macaddr: [u8; 6]) {
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let clocks = CpuClocks::get();
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let mut mdc_clk_div = (clocks.cpu_1x() / MAX_MDC) + 1;
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self.regs.net_cfg.write(
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regs::NetCfg::zeroed()
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.full_duplex(true)
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.gige_en(true)
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.speed(true)
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.no_broadcast(false)
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.multi_hash_en(true)
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// Promiscuous mode (TODO?)
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.copy_all(true)
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// Remove 4-byte Frame CheckSum
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.fcs_remove(true)
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// One of the slower speeds
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.mdc_clk_div((mdc_clk_div >> 4).min(0b111) as u8)
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);
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let macaddr_msbs =
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(u16::from(macaddr[0]) << 8) |
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u16::from(macaddr[1]);
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let macaddr_lsbs =
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(u32::from(macaddr[2]) << 24) |
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(u32::from(macaddr[3]) << 16) |
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(u32::from(macaddr[4]) << 8) |
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u32::from(macaddr[5]);
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self.regs.spec_addr1_top.write(
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regs::SpecAddrTop::zeroed()
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.addr_msbs(macaddr_msbs)
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);
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self.regs.spec_addr1_bot.write(
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regs::SpecAddrBot::zeroed()
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.addr_lsbs(macaddr_lsbs)
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);
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self.regs.dma_cfg.write(
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regs::DmaCfg::zeroed()
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// 1536 bytes
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.ahb_mem_rx_buf_size((MTU >> 6) as u8)
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// 8 KB
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.rx_pktbuf_memsz_sel(0x3)
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// 4 KB
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.tx_pktbuf_memsz_sel(true)
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.csum_gen_offload_en(true)
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// Little-endian
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.ahb_endian_swp_mgmt_en(false)
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// INCR16 AHB burst
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.ahb_fixed_burst_len(0x10)
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);
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self.regs.net_ctrl.write(
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regs::NetCtrl::zeroed()
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.mgmt_port_en(true)
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);
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}
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pub fn start_rx<'rx>(self, rx_list: &'rx mut [rx::DescEntry], rx_buffers: &'rx mut [[u8; MTU]]) -> Eth<rx::DescList<'rx>, TX> {
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let new_self = Eth {
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regs: self.regs,
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rx: rx::DescList::new(rx_list, rx_buffers),
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tx: self.tx,
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};
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let list_addr = new_self.rx.list_addr();
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assert!(list_addr & 0b11 == 0);
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new_self.regs.rx_qbar.write(
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regs::RxQbar::zeroed()
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.rx_q_baseaddr(list_addr >> 2)
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);
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new_self.regs.net_ctrl.modify(|_, w|
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w.rx_en(true)
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);
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new_self
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}
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pub fn start_tx<'tx>(self, tx_list: &'tx mut [tx::DescEntry], tx_buffers: &'tx mut [[u8; MTU]]) -> Eth<RX, tx::DescList<'tx>> {
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let new_self = Eth {
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regs: self.regs,
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rx: self.rx,
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tx: tx::DescList::new(tx_list, tx_buffers),
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};
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let list_addr = &new_self.tx.list_addr();
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assert!(list_addr & 0b11 == 0);
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new_self.regs.tx_qbar.write(
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regs::TxQbar::zeroed()
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.tx_q_baseaddr(list_addr >> 2)
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);
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new_self.regs.net_ctrl.modify(|_, w|
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w.tx_en(true)
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);
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new_self
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}
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fn wait_phy_idle(&self) {
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while !self.regs.net_status.read().phy_mgmt_idle() {}
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}
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pub fn reset_phy(&mut self) -> bool {
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match phy::Phy::find(self) {
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Some(phy) => {
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phy.modify_control(self, |control|
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control.set_reset(true)
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);
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while phy.get_control(self).reset() {
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println!("Wait for PHY reset");
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}
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phy.modify_control(self, |control|
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control.set_autoneg_enable(true)
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.set_restart_autoneg(true)
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);
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// 125 MHz for 1000base-TX
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Self::setup_gem0_clock(TX_1000);
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true
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}
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None => false
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}
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}
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}
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impl<'rx, TX> Eth<rx::DescList<'rx>, TX> {
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pub fn recv_next<'s: 'p, 'p>(&'s mut self) -> Result<Option<rx::PktRef<'p>>, rx::Error> {
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let status = self.regs.rx_status.read();
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if status.hresp_not_ok() {
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// Clear
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self.regs.rx_status.write(
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regs::RxStatus::zeroed()
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.hresp_not_ok(true)
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);
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return Err(rx::Error::HrespNotOk);
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}
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if status.rx_overrun() {
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// Clear
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self.regs.rx_status.write(
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regs::RxStatus::zeroed()
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.rx_overrun(true)
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);
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return Err(rx::Error::RxOverrun);
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}
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if status.buffer_not_avail() {
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// Clear
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self.regs.rx_status.write(
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regs::RxStatus::zeroed()
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.buffer_not_avail(true)
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);
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return Err(rx::Error::BufferNotAvail);
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}
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if status.frame_recd() {
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let result = self.rx.recv_next();
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match result {
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Ok(None) => {
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// No packet, clear status bit
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self.regs.rx_status.write(
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regs::RxStatus::zeroed()
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.frame_recd(true)
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);
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}
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_ => {}
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}
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result
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} else {
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Ok(None)
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}
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}
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}
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impl<'tx, RX> Eth<RX, tx::DescList<'tx>> {
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pub fn send<'s: 'p, 'p>(&'s mut self, length: usize) -> Option<tx::PktRef<'p>> {
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self.tx.send(&mut self.regs, length)
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}
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}
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impl<RX, TX> phy::PhyAccess for Eth<RX, TX> {
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fn read_phy(&mut self, addr: u8, reg: u8) -> u16 {
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self.wait_phy_idle();
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self.regs.phy_maint.write(
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regs::PhyMaint::zeroed()
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.clause_22(true)
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.operation(regs::PhyOperation::Read)
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.phy_addr(addr)
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.reg_addr(reg)
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.must_10(0b10)
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);
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self.wait_phy_idle();
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self.regs.phy_maint.read().data()
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}
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fn write_phy(&mut self, addr: u8, reg: u8, data: u16) {
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self.wait_phy_idle();
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self.regs.phy_maint.write(
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regs::PhyMaint::zeroed()
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.clause_22(true)
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.operation(regs::PhyOperation::Write)
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.phy_addr(addr)
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.reg_addr(reg)
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.must_10(0b10)
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.data(data)
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);
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self.wait_phy_idle();
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}
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}
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