From e1068af9481ff82516477e3ae0e059798a0d4a5c Mon Sep 17 00:00:00 2001
From: Astro <astro@spaceboyz.net>
Date: Thu, 12 Dec 2019 01:02:09 +0100
Subject: [PATCH] zynq::flash: add rdsr1()

---
 src/zynq/flash/mod.rs | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/zynq/flash/mod.rs b/src/zynq/flash/mod.rs
index 2725d37..4fd44d4 100644
--- a/src/zynq/flash/mod.rs
+++ b/src/zynq/flash/mod.rs
@@ -14,6 +14,8 @@ const SINGLE_CAPACITY: u32 = 16 * 1024 * 1024;
 
 /// Instruction: Read Configure Register
 const INST_RDCR: u8 = 0x35;
+/// Instruction: Read Status Register-1
+const INST_RDSR1: u8 = 0x05;
 /// Instruction: Read Identification
 const INST_RDID: u8 = 0x9F;
 
@@ -355,6 +357,14 @@ impl Flash<Manual> {
             .next().unwrap() as u8
     }
 
+    /// Read Status Register-1
+    pub fn rdsr1(&mut self) -> u8 {
+        let args = Some(INST_RDSR1 as u8);
+        self.transfer(args.into_iter(), 2)
+            .bytes_transfer().skip(1)
+            .next().unwrap()
+    }
+
     /// Read Identifiaction
     pub fn rdid(&mut self) -> core::iter::Skip<BytesTransfer<Transfer<core::option::IntoIter<u32>, u32>>> {
         let args = Some((INST_RDID as u32) << 24);