From b50540915d20722a1551146b105886f4e127b889 Mon Sep 17 00:00:00 2001
From: pca006132 <jl@m-labs.hk>
Date: Tue, 26 Jan 2021 11:16:37 +0800
Subject: [PATCH] libcortex_a9: memcpy throughput optimization

---
 libcortex_a9/src/l2c.rs  | 7 ++++++-
 libcortex_a9/src/regs.rs | 2 +-
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/libcortex_a9/src/l2c.rs b/libcortex_a9/src/l2c.rs
index b66d597..49b29f3 100644
--- a/libcortex_a9/src/l2c.rs
+++ b/libcortex_a9/src/l2c.rs
@@ -2,7 +2,9 @@ use libregister::{register, register_at, register_bit, register_bits, RegisterRW
 use super::asm::dmb;
 use volatile_register::RW;
 
-pub fn enable_l2_cache() {
+/// enable L2 cache with specific prefetch offset
+/// prefetch offset requires manual tuning, it seems that 8 is good for ZC706 current settings
+pub fn enable_l2_cache(offset: u8) {
     dmb();
     let regs = RegisterBlock::new();
     // disable L2 cache
@@ -14,6 +16,7 @@ pub fn enable_l2_cache() {
             .double_linefill_en(true)
             .incr_double_linefill_en(true)
             .pref_drop_en(true)
+            .prefetch_offset(offset)
     );
     regs.reg1_aux_control.modify(|_, w| {
         w.early_bresp_en(true)
@@ -326,3 +329,5 @@ register_bit!(reg15_prefetch_ctrl, instr_prefetch_en, 29);
 register_bit!(reg15_prefetch_ctrl, data_prefetch_en, 28);
 register_bit!(reg15_prefetch_ctrl, pref_drop_en, 24);
 register_bit!(reg15_prefetch_ctrl, incr_double_linefill_en, 23);
+register_bits!(reg15_prefetch_ctrl, prefetch_offset, u8, 0, 4);
+
diff --git a/libcortex_a9/src/regs.rs b/libcortex_a9/src/regs.rs
index 398da6d..2b73cfe 100644
--- a/libcortex_a9/src/regs.rs
+++ b/libcortex_a9/src/regs.rs
@@ -173,7 +173,7 @@ impl RegisterRW for ACTLR {
 
 impl ACTLR {
     pub fn enable_smp(&mut self) {
-        self.modify(|_, w| w.smp(true).fw(true));
+        self.modify(|_, w| w.smp(true).fw(true).alloc_one_way(true));
     }
 
     pub fn enable_prefetch(&mut self) {