From 04e816d99ed326c7430ca156145ac2199dd33cce Mon Sep 17 00:00:00 2001
From: Astro <astro@spaceboyz.net>
Date: Sun, 3 Nov 2019 02:01:42 +0100
Subject: [PATCH] zynq::slcr: fix a bitfield index

that didn't solve our problems.
---
 src/zynq/slcr.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/zynq/slcr.rs b/src/zynq/slcr.rs
index a95fd42..154224a 100644
--- a/src/zynq/slcr.rs
+++ b/src/zynq/slcr.rs
@@ -376,7 +376,7 @@ register_bits!(gem_clk_ctrl,
                divisor, u8, 8, 13);
 register_bits_typed!(gem_clk_ctrl,
                      /// Source to generate the ref clock
-                     srcsel, u8, PllSource, 4, 5);
+                     srcsel, u8, PllSource, 4, 6);
 register_bit!(gem_clk_ctrl,
               /// SMC reference clock control
               clkact, 0);