forked from M-Labs/artiq-zynq
273 lines
8.5 KiB
Python
273 lines
8.5 KiB
Python
from operator import attrgetter
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from migen import *
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from migen.genlib.cdc import MultiReg
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from migen_axi.interconnect import axi
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from misoc.interconnect.csr import *
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from artiq.gateware import rtio
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OUT_BURST_LEN = 10
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IN_BURST_LEN = 4
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class Engine(Module, AutoCSR):
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def __init__(self, bus, user):
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self.addr_base = CSRStorage(32)
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self.trig_count = CSRStatus(32)
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self.write_count = CSRStatus(32)
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self.trigger_stb = Signal()
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# Dout : Data received from CPU, output by DMA module
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# Din : Data driven into DMA module, written into CPU
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# When stb assert, index shows word being read/written, dout/din holds
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# data
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#
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# Cycle:
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# trigger_stb pulsed at start
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# Then out_burst_len words are strobed out of dout
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# Then, when din_ready is high, in_burst_len words are strobed in to din
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self.dout_stb = Signal()
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self.din_stb = Signal()
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self.dout_index = Signal(max=16)
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self.din_index = Signal(max=16)
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self.din_ready = Signal()
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self.dout = Signal(64)
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self.din = Signal(64)
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###
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self.sync += If(self.trigger_stb, self.trig_count.status.eq(self.trig_count.status+1))
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self.comb += [
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user.aruser.eq(0x1f),
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user.awuser.eq(0x1f)
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]
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ar, aw, w, r, b = attrgetter("ar", "aw", "w", "r", "b")(bus)
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### Read
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self.comb += [
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ar.addr.eq(self.addr_base.storage),
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self.dout.eq(r.data),
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r.ready.eq(1),
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ar.burst.eq(axi.Burst.incr.value),
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ar.len.eq(OUT_BURST_LEN-1), # Number of transfers in burst (0->1 transfer, 1->2 transfers...)
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ar.size.eq(3), # Width of burst: 3 = 8 bytes = 64 bits
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ar.cache.eq(0xf),
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]
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# read control
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self.submodules.read_fsm = read_fsm = FSM(reset_state="IDLE")
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read_fsm.act("IDLE",
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If(self.trigger_stb,
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ar.valid.eq(1),
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If(ar.ready,
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NextState("READ")
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).Else(
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NextState("READ_START")
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)
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)
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)
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read_fsm.act("READ_START",
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ar.valid.eq(1),
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If(ar.ready,
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NextState("READ"),
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)
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)
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read_fsm.act("READ",
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ar.valid.eq(0),
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If(r.last & r.valid,
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NextState("IDLE")
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)
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)
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self.sync += [
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If(read_fsm.ongoing("IDLE"),
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self.dout_index.eq(0)
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).Else(If(r.valid & read_fsm.ongoing("READ"),
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self.dout_index.eq(self.dout_index+1)
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)
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)
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]
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self.comb += self.dout_stb.eq(r.valid & r.ready)
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### Write
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self.comb += [
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w.data.eq(self.din),
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aw.addr.eq(self.addr_base.storage+96),
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w.strb.eq(0xff),
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aw.burst.eq(axi.Burst.incr.value),
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aw.len.eq(IN_BURST_LEN-1), # Number of transfers in burst minus 1
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aw.size.eq(3), # Width of burst: 3 = 8 bytes = 64 bits
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aw.cache.eq(0xf),
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b.ready.eq(1),
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]
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# write control
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self.submodules.write_fsm = write_fsm = FSM(reset_state="IDLE")
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write_fsm.act("IDLE",
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w.valid.eq(0),
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aw.valid.eq(0),
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If(self.trigger_stb,
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aw.valid.eq(1),
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If(aw.ready, # assumes aw.ready is not randomly deasserted
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NextState("DATA_WAIT")
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).Else(
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NextState("AW_READY_WAIT")
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)
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)
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)
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write_fsm.act("AW_READY_WAIT",
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aw.valid.eq(1),
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If(aw.ready,
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NextState("DATA_WAIT"),
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)
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)
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write_fsm.act("DATA_WAIT",
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aw.valid.eq(0),
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If(self.din_ready,
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w.valid.eq(1),
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NextState("WRITE")
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)
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)
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write_fsm.act("WRITE",
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w.valid.eq(1),
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If(w.ready & w.last,
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NextState("IDLE")
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)
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)
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self.sync += If(w.ready & w.valid, self.write_count.status.eq(self.write_count.status+1))
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self.sync += [
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If(write_fsm.ongoing("IDLE"),
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self.din_index.eq(0)
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),
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If(w.ready & w.valid, self.din_index.eq(self.din_index+1))
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]
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self.comb += [
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w.last.eq(0),
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If(self.din_index==aw.len, w.last.eq(1))
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]
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self.comb += self.din_stb.eq(w.valid & w.ready)
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class KernelInitiator(Module, AutoCSR):
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def __init__(self, tsc, bus, user, evento):
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# Core is disabled upon reset to avoid spurious triggering if evento toggles from e.g. boot code.
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self.enable = CSRStorage()
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self.counter = CSRStatus(64)
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self.counter_update = CSR()
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self.o_status = CSRStatus(3)
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self.i_status = CSRStatus(4)
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self.submodules.engine = Engine(bus, user)
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self.cri = rtio.cri.Interface()
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###
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evento_stb = Signal()
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evento_latched = Signal()
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evento_latched_d = Signal()
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self.specials += MultiReg(evento, evento_latched)
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self.sync += evento_latched_d.eq(evento_latched)
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self.comb += self.engine.trigger_stb.eq(self.enable.storage & (evento_latched != evento_latched_d))
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cri = self.cri
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cmd = Signal(8)
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cmd_write = Signal()
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cmd_read = Signal()
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self.comb += [
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cmd_write.eq(cmd == 0),
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cmd_read.eq(cmd == 1)
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]
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out_len = Signal(8)
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dout_cases = {}
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dout_cases[0] = [
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cmd.eq(self.engine.dout[:8]),
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out_len.eq(self.engine.dout[8:16]),
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cri.chan_sel.eq(self.engine.dout[40:]),
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cri.o_address.eq(self.engine.dout[32:40])
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]
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for i in range(8):
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target = cri.o_data[i*64:(i+1)*64]
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dout_cases[0] += [If(i >= self.engine.dout[8:16], target.eq(0))]
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dout_cases[1] = [
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cri.o_timestamp.eq(self.engine.dout),
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cri.i_timeout.eq(self.engine.dout)
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]
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for i in range(8):
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target = cri.o_data[i*64:(i+1)*64]
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dout_cases[i+2] = [target.eq(self.engine.dout)]
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self.sync += [
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cri.cmd.eq(rtio.cri.commands["nop"]),
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If(self.engine.dout_stb,
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Case(self.engine.dout_index, dout_cases),
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If(self.engine.dout_index == out_len + 2,
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If(cmd_write, cri.cmd.eq(rtio.cri.commands["write"])),
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If(cmd_read, cri.cmd.eq(rtio.cri.commands["read"]))
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)
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)
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]
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# If input event, wait for response before allow input data to be
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# sampled
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# TODO: If output, wait for wait flag clear
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RTIO_I_STATUS_WAIT_STATUS = 4
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RTIO_O_STATUS_WAIT = 1
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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If(self.engine.trigger_stb, NextState("WAIT_OUT_CYCLE"))
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)
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fsm.act("WAIT_OUT_CYCLE",
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self.engine.din_ready.eq(0),
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If(self.engine.dout_stb & cmd_write & (self.engine.dout_index == out_len + 2),
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NextState("WAIT_READY")
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),
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# for some reason read requires some delay until the next state
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If(self.engine.dout_stb & cmd_read & (self.engine.dout_index == out_len + 3),
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NextState("WAIT_READY")
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)
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)
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fsm.act("WAIT_READY",
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If(cmd_read & (cri.i_status & RTIO_I_STATUS_WAIT_STATUS == 0) \
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| cmd_write & ~(cri.o_status & RTIO_O_STATUS_WAIT),
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self.engine.din_ready.eq(1),
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NextState("IDLE")
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)
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)
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din_cases_cmdwrite = {
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0: [self.engine.din.eq((1<<16) | cri.o_status)],
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1: [self.engine.din.eq(0)],
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}
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din_cases_cmdread = {
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0: [self.engine.din[:32].eq((1<<16) | cri.i_status), self.engine.din[32:].eq(cri.i_data)],
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1: [self.engine.din.eq(cri.i_timestamp)]
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}
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self.comb += [
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If(cmd_read, Case(self.engine.din_index, din_cases_cmdread)),
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If(cmd_write, Case(self.engine.din_index, din_cases_cmdwrite)),
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]
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# CRI CSRs
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self.sync += If(self.counter_update.re, self.counter.status.eq(tsc.full_ts_cri))
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self.comb += [
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self.o_status.status.eq(self.cri.o_status),
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self.i_status.status.eq(self.cri.i_status),
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]
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