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artiq-zynq
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576 Commits 3 Branches 0 Tags 1.8 MiB
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54 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq ea96cf96d3 dma: add simulation test (WIP) 2020-07-13 12:04:10 +08:00
Sebastien Bourdeauducq 10888cc6c6 dma: remove unneeded import 2020-07-13 10:42:02 +08:00
Sebastien Bourdeauducq a7073edf79 add DMA core (untested) 2020-07-13 10:37:17 +08:00
Sebastien Bourdeauducq e3ff21b1b5 create gateware folder 2020-07-11 17:49:54 +08:00