jcoates
/
artiq-zynq
forked from M-Labs/artiq-zynq
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

zc706: not actually ultrascale

This commit is contained in:
mwojcik 2021-11-29 12:48:45 +08:00
parent ada3f2e704
commit e045837b67
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/gateware/zc706.py
View File

@ -399,7 +399,7 @@ class _SatelliteBase(SoCCore):
self.submodules.siphaser = SiPhaser7Series( self.submodules.siphaser = SiPhaser7Series(
si5324_clkin=platform.request("si5324_clkin"), si5324_clkin=platform.request("si5324_clkin"),
rx_synchronizer=self.rx_synchronizer, rx_synchronizer=self.rx_synchronizer,
ultrascale=True, ultrascale=False,
rtio_clk_freq=self.drtio_transceiver.rtio_clk_freq) rtio_clk_freq=self.drtio_transceiver.rtio_clk_freq)
platform.add_false_path_constraints( platform.add_false_path_constraints(
self.ps7.cd_sys.clk, self.siphaser.mmcm_freerun_output) self.ps7.cd_sys.clk, self.siphaser.mmcm_freerun_output)