forked from M-Labs/artiq-zynq
KasliSoC satellite: fix serdes timing
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@ -342,6 +342,8 @@ class GenericSatellite(SoCCore):
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self.crg = self.ps7 # HACK for eem_7series to find the clock
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self.crg.cd_sys = self.sys_crg.cd_sys
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fix_serdes_timing_path(platform)
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self.rtio_channels = []
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has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
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if has_grabber:
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