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Revert "kasli-soc: work around I2C breakage (#130)" 

This reverts commit f1fd55dee5.
This commit is contained in:
Sebastien Bourdeauducq 2021-07-30 16:55:06 +08:00
parent cbcda286dc
commit 8128dc0b56
2 changed files with 12 additions and 3 deletions
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11
src/gateware/kasli_soc.py
View File

@ -28,6 +28,15 @@ class RTIOCRG(Module, AutoCSR):
self.clock_domains.cd_rtio = ClockDomain() self.clock_domains.cd_rtio = ClockDomain()
self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True) self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
clk_synth = platform.request("cdr_clk_clean_fabric")
clk_synth_se = Signal()
platform.add_period_constraint(clk_synth.p, 8.0)
self.specials += [
Instance("IBUFGDS",
p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE",
i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se),
]
pll_locked = Signal() pll_locked = Signal()
rtio_clk = Signal() rtio_clk = Signal()
rtiox4_clk = Signal() rtiox4_clk = Signal()
@ -38,7 +47,7 @@ class RTIOCRG(Module, AutoCSR):
p_BANDWIDTH="HIGH", p_BANDWIDTH="HIGH",
p_REF_JITTER1=0.001, p_REF_JITTER1=0.001,
p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=8.0, p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=8.0,
i_CLKIN2=ClockSignal(), i_CLKIN2=clk_synth_se,
# Warning: CLKINSEL=0 means CLKIN2 is selected # Warning: CLKINSEL=0 means CLKIN2 is selected
i_CLKINSEL=0, i_CLKINSEL=0,

4
src/runtime/src/main.rs
View File

@ -199,9 +199,9 @@ pub fn main_core0() {
info!("detected gateware: {}", identifier_read(&mut [0; 64])); info!("detected gateware: {}", identifier_read(&mut [0; 64]));
i2c::init(); i2c::init();
/*#[cfg(feature = "target_kasli_soc")] #[cfg(feature = "target_kasli_soc")]
si5324::setup(unsafe { (&mut i2c::I2C_BUS).as_mut().unwrap() }, si5324::setup(unsafe { (&mut i2c::I2C_BUS).as_mut().unwrap() },
&SI5324_SETTINGS, si5324::Input::Ckin1).expect("cannot initialize Si5324");*/ &SI5324_SETTINGS, si5324::Input::Ckin1).expect("cannot initialize Si5324");
let cfg = match Config::new() { let cfg = match Config::new() {
Ok(cfg) => cfg, Ok(cfg) => cfg,