forked from M-Labs/artiq-zynq
drtio: port 64-bit padding from mainline
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parent
efc432352e
commit
57d7f01b04
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@ -153,11 +153,10 @@ pub fn send(linkno: u8, packet: &Packet) -> Result<(), Error> {
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packet.write_to(&mut writer)?;
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let padding = 4 - (writer.position() % 4);
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if padding != 4 {
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for _ in 0..padding {
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writer.write_u8(0)?;
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}
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// Pad till offset 4, insert checksum there
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let padding = (12 - (writer.position() % 8)) % 8;
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for _ in 0..padding {
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writer.write_u8(0)?;
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}
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let checksum = crc::crc32::checksum_ieee(&writer.get_ref()[0..writer.position()]);
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@ -124,11 +124,10 @@ pub async fn send(linkno: u8, packet: &Packet) -> Result<(), Error> {
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packet.write_to(&mut writer)?;
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let padding = 4 - (writer.position() % 4);
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if padding != 4 {
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for _ in 0..padding {
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writer.write_u8(0)?;
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}
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// Pad till offset 4, insert checksum there
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let padding = (12 - (writer.position() % 8)) % 8;
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for _ in 0..padding {
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writer.write_u8(0)?;
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}
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let checksum = crc::crc32::checksum_ieee(&writer.get_ref()[0..writer.position()]);
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