forked from M-Labs/artiq-zynq
23 lines
914 B
Python
23 lines
914 B
Python
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from misoc.integration import cpu_interface
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def write_csr_file(soc, filename):
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with open(filename, "w") as f:
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f.write(cpu_interface.get_csr_rust(
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soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants()))
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def write_mem_file(soc, filename):
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with open(filename, "w") as f:
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f.write(cpu_interface.get_mem_rust(
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soc.get_memory_regions(), soc.get_memory_groups(), None))
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def write_rustc_cfg_file(soc, filename):
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with open(filename, "w") as f:
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for name, origin, busword, obj in soc.get_csr_regions():
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f.write("has_{}\n".format(name.lower()))
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for name, value in soc.get_constants():
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if name.upper().startswith("CONFIG_"):
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if value is None:
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f.write("{}\n".format(name.lower()[7:]))
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else:
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f.write("{}=\"{}\"\n".format(name.lower()[7:], str(value)))
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