forked from M-Labs/thermostat
update code to use stm32f4xx-hal 0.10.1 API
This commit is contained in:
parent
e6f63ec940
commit
1b2f2f3888
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@ -41,7 +41,7 @@ impl StoreBackend for FlashBackend {
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fn program(&mut self, offset: usize, payload: &[u8]) -> Result<(), Self::Error> {
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self.flash.unlocked()
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.program(get_offset() + offset, payload.iter().cloned())
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.program(get_offset() + offset, payload.iter())
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}
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fn backup_space(&self) -> &'static mut [u8] {
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@ -1,6 +1,6 @@
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#![cfg_attr(not(test), no_std)]
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#![cfg_attr(not(test), no_main)]
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#![feature(maybe_uninit_extra, maybe_uninit_ref, asm)]
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#![feature(maybe_uninit_extra, asm)]
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#![cfg_attr(test, allow(unused))]
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// TODO: #![deny(warnings, unused)]
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@ -5,14 +5,14 @@ use core::cell::RefCell;
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use cortex_m::interrupt::{CriticalSection, Mutex};
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use stm32f4xx_hal::{
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rcc::Clocks,
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stm32::{interrupt, Peripherals, ETHERNET_MAC, ETHERNET_DMA},
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pac::{interrupt, Peripherals, ETHERNET_MAC, ETHERNET_DMA},
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};
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use smoltcp::wire::{EthernetAddress, Ipv4Address, Ipv4Cidr};
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use smoltcp::iface::{
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EthernetInterfaceBuilder, EthernetInterface,
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NeighborCache, Routes,
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};
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use stm32_eth::{Eth, RingEntry, PhyAddress, RxDescriptor, TxDescriptor};
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use stm32_eth::{Eth, RingEntry, RxDescriptor, TxDescriptor};
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use crate::command_parser::Ipv4Config;
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use crate::pins::EthernetPins;
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@ -48,7 +48,6 @@ pub fn run<F>(
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let mut eth_dev = Eth::new(
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ethernet_mac, ethernet_dma,
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&mut rx_ring[..], &mut tx_ring[..],
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PhyAddress::_0,
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clocks,
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eth_pins,
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).unwrap();
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76
src/pins.rs
76
src/pins.rs
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@ -16,8 +16,8 @@ use stm32f4xx_hal::{
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otg_fs::USB,
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rcc::Clocks,
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pwm::{self, PwmChannels},
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spi::{Spi, NoMiso},
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stm32::{
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spi::{Spi, NoMiso, TransferModeNormal},
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pac::{
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ADC1,
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GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG,
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I2C1,
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@ -25,6 +25,7 @@ use stm32f4xx_hal::{
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SPI2, SPI4, SPI5,
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TIM1, TIM3,
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},
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timer::Timer,
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time::U32Ext,
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};
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use eeprom24x::{self, Eeprom24x};
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@ -36,8 +37,8 @@ use crate::{
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pub type Eeprom = Eeprom24x<
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I2c<I2C1, (
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PB8<AlternateOD<stm32f4xx_hal::gpio::AF4>>,
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PB9<AlternateOD<stm32f4xx_hal::gpio::AF4>>
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PB8<AlternateOD<{ stm32f4xx_hal::gpio::AF4 }>>,
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PB9<AlternateOD<{ stm32f4xx_hal::gpio::AF4 }>>
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)>,
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eeprom24x::page_size::B8,
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eeprom24x::addr_size::OneByte
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@ -45,8 +46,6 @@ pub type Eeprom = Eeprom24x<
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pub type EthernetPins = EthPins<
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PA1<Input<Floating>>,
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PA2<Input<Floating>>,
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PC1<Input<Floating>>,
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PA7<Input<Floating>>,
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PB11<Input<Floating>>,
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PG13<Input<Floating>>,
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@ -86,10 +85,10 @@ impl ChannelPins for Channel1 {
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}
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/// SPI peripheral used for communication with the ADC
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pub type AdcSpi = Spi<SPI2, (PB10<Alternate<AF5>>, PB14<Alternate<AF5>>, PB15<Alternate<AF5>>)>;
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pub type AdcSpi = Spi<SPI2, (PB10<Alternate<AF5>>, PB14<Alternate<AF5>>, PB15<Alternate<AF5>>), TransferModeNormal>;
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pub type AdcNss = PB12<Output<PushPull>>;
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type Dac0Spi = Spi<SPI4, (PE2<Alternate<AF5>>, NoMiso, PE6<Alternate<AF5>>)>;
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type Dac1Spi = Spi<SPI5, (PF7<Alternate<AF5>>, NoMiso, PF9<Alternate<AF5>>)>;
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type Dac0Spi = Spi<SPI4, (PE2<Alternate<AF5>>, NoMiso, PE6<Alternate<AF5>>), TransferModeNormal>;
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type Dac1Spi = Spi<SPI5, (PF7<Alternate<AF5>>, NoMiso, PF9<Alternate<AF5>>), TransferModeNormal>;
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pub type PinsAdc = Adc<ADC1>;
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pub struct ChannelPinSet<C: ChannelPins> {
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@ -192,15 +191,13 @@ impl Pins {
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let leds = Leds::new(gpiod.pd9, gpiod.pd10.into_push_pull_output(), gpiod.pd11.into_push_pull_output());
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let eeprom_scl = gpiob.pb8.into_alternate_af4().set_open_drain();
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let eeprom_sda = gpiob.pb9.into_alternate_af4().set_open_drain();
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let eeprom_i2c = I2c::i2c1(i2c1, (eeprom_scl, eeprom_sda), 400.khz(), clocks);
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let eeprom_scl = gpiob.pb8.into_alternate().set_open_drain();
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let eeprom_sda = gpiob.pb9.into_alternate().set_open_drain();
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let eeprom_i2c = I2c::new(i2c1, (eeprom_scl, eeprom_sda), 400.khz(), clocks);
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let eeprom = Eeprom24x::new_24x02(eeprom_i2c, eeprom24x::SlaveAddr::default());
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let eth_pins = EthPins {
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ref_clk: gpioa.pa1,
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md_io: gpioa.pa2,
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md_clk: gpioc.pc1,
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crs: gpioa.pa7,
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tx_en: gpiob.pb11,
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tx_d0: gpiog.pg13,
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@ -213,8 +210,8 @@ impl Pins {
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usb_global: otg_fs_global,
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usb_device: otg_fs_device,
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usb_pwrclk: otg_fs_pwrclk,
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pin_dm: gpioa.pa11.into_alternate_af10(),
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pin_dp: gpioa.pa12.into_alternate_af10(),
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pin_dm: gpioa.pa11.into_alternate(),
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pin_dp: gpioa.pa12.into_alternate(),
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hclk: clocks.hclk(),
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};
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@ -230,14 +227,14 @@ impl Pins {
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mosi: PB15<M3>,
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) -> AdcSpi
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{
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let sck = sck.into_alternate_af5();
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let miso = miso.into_alternate_af5();
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let mosi = mosi.into_alternate_af5();
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Spi::spi2(
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let sck = sck.into_alternate();
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let miso = miso.into_alternate();
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let mosi = mosi.into_alternate();
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Spi::new(
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spi2,
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(sck, miso, mosi),
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crate::ad7172::SPI_MODE,
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crate::ad7172::SPI_CLOCK.into(),
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crate::ad7172::SPI_CLOCK,
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clocks
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)
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}
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@ -246,13 +243,13 @@ impl Pins {
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clocks: Clocks, spi4: SPI4,
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sclk: PE2<M1>, sync: PE4<M2>, sdin: PE6<M3>
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) -> (Dac0Spi, <Channel0 as ChannelPins>::DacSync) {
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let sclk = sclk.into_alternate_af5();
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let sdin = sdin.into_alternate_af5();
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let spi = Spi::spi4(
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let sclk = sclk.into_alternate();
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let sdin = sdin.into_alternate();
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let spi = Spi::new(
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spi4,
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(sclk, NoMiso, sdin),
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(sclk, NoMiso {}, sdin),
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crate::ad5680::SPI_MODE,
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crate::ad5680::SPI_CLOCK.into(),
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crate::ad5680::SPI_CLOCK,
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clocks
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);
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let sync = sync.into_push_pull_output();
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@ -264,13 +261,13 @@ impl Pins {
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clocks: Clocks, spi5: SPI5,
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sclk: PF7<M1>, sync: PF6<M2>, sdin: PF9<M3>
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) -> (Dac1Spi, <Channel1 as ChannelPins>::DacSync) {
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let sclk = sclk.into_alternate_af5();
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let sdin = sdin.into_alternate_af5();
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let spi = Spi::spi5(
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let sclk = sclk.into_alternate();
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let sdin = sdin.into_alternate();
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let spi = Spi::new(
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spi5,
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(sclk, NoMiso, sdin),
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(sclk, NoMiso {}, sdin),
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crate::ad5680::SPI_MODE,
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crate::ad5680::SPI_CLOCK.into(),
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crate::ad5680::SPI_CLOCK,
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clocks
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);
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let sync = sync.into_push_pull_output();
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@ -307,21 +304,22 @@ impl PwmPins {
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pin.enable();
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}
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let channels = (
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max_v0.into_alternate_af2(),
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max_v1.into_alternate_af2(),
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max_v0.into_alternate(),
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max_v1.into_alternate(),
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);
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let (mut max_v0, mut max_v1) = pwm::tim3(tim3, channels, clocks, freq);
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//let (mut max_v0, mut max_v1) = pwm::tim3(tim3, channels, clocks, freq);
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let (mut max_v0, mut max_v1) = Timer::new(tim3, &clocks).pwm(channels, freq);
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init_pwm_pin(&mut max_v0);
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init_pwm_pin(&mut max_v1);
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let channels = (
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max_i_pos0.into_alternate_af1(),
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max_i_pos1.into_alternate_af1(),
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max_i_neg0.into_alternate_af1(),
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max_i_neg1.into_alternate_af1(),
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max_i_pos0.into_alternate(),
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max_i_pos1.into_alternate(),
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max_i_neg0.into_alternate(),
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max_i_neg1.into_alternate(),
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);
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let (mut max_i_pos0, mut max_i_pos1, mut max_i_neg0, mut max_i_neg1) =
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pwm::tim1(tim1, channels, clocks, freq);
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Timer::new(tim1, &clocks).pwm(channels, freq);
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init_pwm_pin(&mut max_i_pos0);
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init_pwm_pin(&mut max_i_neg0);
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init_pwm_pin(&mut max_i_pos1);
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@ -24,14 +24,14 @@ const TCP_TX_BUFFER_SIZE: usize = 2048;
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/// Contains a number of server sockets that get all sent the same
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/// data (through `fmt::Write`).
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pub struct Server<'a, 'b, S> {
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net: EthernetInterface<'a, 'a, 'a, &'a mut stm32_eth::Eth<'static, 'static>>,
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sockets: SocketSet<'b, 'b, 'b>,
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net: EthernetInterface<'a, &'a mut stm32_eth::Eth<'static, 'static>>,
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sockets: SocketSet<'b>,
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states: [SocketState<S>; SOCKET_COUNT],
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}
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impl<'a, 'b, S: Default> Server<'a, 'b, S> {
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/// Run a server with stack-allocated sockets
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pub fn run<F>(net: EthernetInterface<'a, 'a, 'a, &'a mut stm32_eth::Eth<'static, 'static>>, f: F)
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pub fn run<F>(net: EthernetInterface<'a, &'a mut stm32_eth::Eth<'static, 'static>>, f: F)
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where
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F: FnOnce(&mut Server<'a, '_, S>),
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{
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@ -18,8 +18,10 @@ static TIMER_MS: Mutex<RefCell<u32>> = Mutex::new(RefCell::new(0));
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/// Setup SysTick exception
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pub fn setup(syst: SYST, clocks: Clocks) {
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let mut timer = Timer::syst(syst, TIMER_RATE.hz(), clocks);
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timer.listen(TimerEvent::TimeOut);
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let timer = Timer::syst(syst, &clocks);
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let mut countdown = timer.start_count_down(TIMER_RATE.hz());
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countdown.listen(TimerEvent::TimeOut);
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}
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/// SysTick exception (Timer)
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