2 Commits (33d81cdbdc79cca36e292f7cdfd22aeb9126f679)

Author	SHA1	Message	Date
Harry Ho	fa0b190234	[WIP] Add preliminary ARTIQ scripts for ST1, ST2 ... * For ST2, add the argument `ttl_use_fpga=true` to disable generating 111ns pulses on the TTLs.	2021-03-09 17:02:10 +08:00
Harry Ho	a0d92497a9	Add ARTIQ device DB	2021-03-09 09:54:33 +08:00