Harry Wu

htgazurex1212 commented on pull request M-Labs/zynq-rs#141

2025-07-17 18:34:48 +08:00

WIP: Replacing the Linked List Allocator

cc @LPTK

htgazurex1212 pushed to HTGAzureX1212/malloc at htgazurex1212/zynq-rs

2025-07-17 12:24:22 +08:00

1cf101e05c primitive malloc/free bench

htgazurex1212 pushed to HTGAzureX1212/malloc at htgazurex1212/zynq-rs

2025-07-16 22:26:52 +08:00

885831b3f1 chore: stub for benchmarks

htgazurex1212 commented on pull request M-Labs/zynq-rs#141

2025-07-13 13:33:40 +08:00

WIP: Replacing the Linked List Allocator

It's IPv6 only. Send your complaints to your ISP, ICANN, APNIC, etc.

I got IPv6 working using Cloudflare WARP... now it's timing out.

htgazurex1212 commented on pull request M-Labs/zynq-rs#141

2025-07-13 09:46:41 +08:00

WIP: Replacing the Linked List Allocator

It's IPv6 only. Send your complaints to your ISP, ICANN, APNIC, etc.

Right, my ISP does not support IPv6 at all it seems. >.<

htgazurex1212 commented on pull request M-Labs/zynq-rs#141

2025-07-12 20:26:50 +08:00

WIP: Replacing the Linked List Allocator

Maybe it is a me-issue for running this on a Saturday?

No. Which host? Did you turn on the ZC706 using the network power switch?

rpi-4.m-labs.hk at port 22 (still running the…

htgazurex1212 commented on pull request M-Labs/zynq-rs#141

2025-07-12 13:05:22 +08:00

WIP: Replacing the Linked List Allocator

Please run the full ARTIQ test suite on ZC706 hardware with this patch.

@sb10q, how could I get my hands on this hardware for testing?

https://git.m-labs.hk/M-Labs/zynq-rs/s…

htgazurex1212 pushed to master at htgazurex1212/artiq-zynq

2025-07-12 11:29:28 +08:00

9e6b06250a cargo fmt

58e54ec7af rtio init: wait for comms to acknowledge the reset

Compare 2 commits »

htgazurex1212 pushed to HTGAzureX1212/malloc at htgazurex1212/zynq-rs

2025-07-11 19:10:08 +08:00

02a9701655 ram: FLLEN = 24, SLLEN = 16

htgazurex1212 commented on pull request M-Labs/zynq-rs#141

2025-07-11 19:09:34 +08:00

WIP: Replacing the Linked List Allocator

I apologize for the unthoughtful response (I was still busy preparing for the math exam today 😅).

Well, the maximum FLLEN possible is 27 (as we have 128 MiB heaps), and it seems like…

htgazurex1212 pushed to HTGAzureX1212/malloc at htgazurex1212/zynq-rs

2025-07-10 22:01:18 +08:00

58996c415b ram: use <32, 32> instead

htgazurex1212 commented on pull request M-Labs/zynq-rs#141

2025-07-10 22:01:07 +08:00

WIP: Replacing the Linked List Allocator

No particular reason. Switched to (32, 32) now.

htgazurex1212 pushed to HTGAzureX1212/malloc at htgazurex1212/zynq-rs

2025-07-10 15:07:31 +08:00

8e794c9378 ram: subtraction instead of .offset_from()

htgazurex1212 commented on pull request M-Labs/zynq-rs#141

2025-07-10 14:54:16 +08:00

WIP: Replacing the Linked List Allocator

Please run the full ARTIQ test suite on ZC706 hardware with this patch.

@sb10q, how could I get my hands on this hardware for testing?

https://git.m-labs.hk/M-Labs/zynq-rs/s…

htgazurex1212 commented on pull request M-Labs/zynq-rs#141

2025-07-10 14:47:16 +08:00

WIP: Replacing the Linked List Allocator

Please run the full ARTIQ test suite on ZC706 hardware with this patch.

@sb10q, how could I get my hands on this hardware for testing?

htgazurex1212 pushed to HTGAzureX1212/malloc at htgazurex1212/zynq-rs

2025-07-10 14:44:40 +08:00

82da772b41 ram: .addr(), add mut for __heap1_start

htgazurex1212 commented on pull request M-Labs/zynq-rs#141

2025-07-10 14:41:38 +08:00

WIP: Replacing the Linked List Allocator

Commits squashed.

htgazurex1212 pushed to HTGAzureX1212/malloc at htgazurex1212/zynq-rs

2025-07-10 14:39:27 +08:00

d8b6ca2f74 ram: use rlsf allocator

htgazurex1212 pushed to HTGAzureX1212/malloc at htgazurex1212/zynq-rs

2025-07-10 14:37:02 +08:00

91b23c4dbc ram: oops, values vs addresses...

htgazurex1212 commented on pull request M-Labs/zynq-rs#141

2025-07-10 14:20:28 +08:00

WIP: Replacing the Linked List Allocator

I see. A new syntax a day for me indeed.