mmu: pass l2 table instead of raw address

libcortex_a9/src/mmu.rs

@@ -94,7 +94,8 @@ impl L1Entry {
     }
 
     #[inline(always)]
-    pub fn from_l2_page_table(page_table_base: u32, page_table: L1PointToL2Table) -> Self {
+    pub fn from_l2_page_table(l2_table: &L2Table, page_table: L1PointToL2Table) -> Self {
+        let page_table_base = l2_table.get_base_addr();
         // Must be aligned to 1024 bytes
         assert!(page_table_base & 0x3ff == 0);
         let mut entry = L1Entry(page_table_base);
@@ -557,18 +558,16 @@ impl L1Table {
         result
     }
 
-    pub fn link_l2_page_table(&mut self, virtual_addr: u32, page_table_base: u32) {
+    pub fn link_l2_page_table(&mut self, virtual_addr: u32, l2_table: &L2Table) {
+        assert!(virtual_addr & 0x000f_ffff == 0);
         let index = (virtual_addr >> 20) as usize;
         let entry = L1Entry::from_l2_page_table(
-            page_table_base,
+            l2_table,
             // hardcoded domain to match other L1 entries in DDR space
             L1PointToL2Table { domain: 0b1111 },
         );
         self.table[index] = entry;
-        tlbimva(virtual_addr);
-        bpiall();
-        dsb();
-        isb();
+        invalidate_section(virtual_addr);
     }
 }
 
@@ -664,8 +663,8 @@ pub fn remap_section(virtual_addr: u32, new_physical_base: u32) {
     L1Table::get().remap_section(virtual_addr, new_physical_base);
 }
 
-pub fn link_l2_page_table(virtual_addr: u32, page_table_base: u32) {
-    L1Table::get().link_l2_page_table(virtual_addr, page_table_base);
+pub fn link_l2_page_table(virtual_addr: u32, l2_table: &L2Table) {
+    L1Table::get().link_l2_page_table(virtual_addr, l2_table);
 }
 
 #[inline(always)]