htgazurex1212/zynq-rs
1
0
Fork 0
forked from M-Labs/zynq-rs
Code Pull Requests Activity

cargo fmt

Browse Source
This commit is contained in:
Sebastien Bourdeauducq
2026-02-24 23:20:20 +08:00
parent 7b2e37351d
commit 6cec8914f8
1 changed files with 5 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
libcortex_a9/src/mmu.rs
View File

@@ -89,7 +89,7 @@ impl L1Entry {
assert!(phys_base & 0x000f_ffff == 0);
let mut entry = L1Entry(phys_base);
entry.set_section(section);
entry.set_section(section);
entry
}
@@ -154,7 +154,7 @@ pub struct L2Section {
pub access: AccessPermissions,
pub cacheable: bool,
pub bufferable: bool,
pub large: bool, // true for 64KB pages, false for 4KB
pub large: bool, // true for 64KB pages, false for 4KB
}
const L2_TABLE_SIZE: usize = 256;
@@ -562,7 +562,7 @@ impl L1Table {
let entry = L1Entry::from_l2_page_table(
page_table_base,
// hardcoded domain to match other L1 entries in DDR space
L1PointToL2Table { domain: 0b1111 }
L1PointToL2Table { domain: 0b1111 },
);
self.table[index] = entry;
tlbimva(virtual_addr);
@@ -595,8 +595,7 @@ impl L2Table {
bufferable: true,
};
for i in 0..L2_TABLE_SIZE {
self.l2_table[i] =
L2Entry::from_section(base_addr + (i as u32 * 4096), small_flat_page);
self.l2_table[i] = L2Entry::from_section(base_addr + (i as u32 * 4096), small_flat_page);
}
invalidate_section(base_addr);
}
@@ -679,4 +678,4 @@ fn invalidate_section(virtual_addr: u32) {
bpiall();
dsb();
isb();
}
}