forked from M-Labs/artiq-zynq
cargo fmt
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@@ -8,7 +8,7 @@ use dyld::{Library, elf::EXIDX_Entry};
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use libboard_zynq::{gic, mpcore};
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use libcortex_a9::{asm::{dsb, isb},
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cache::{bpiall, dcci_slice, iciallu},
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mmu::{link_l2_page_table, L2Table},
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mmu::{L2Table, link_l2_page_table},
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sync_channel};
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use libsupport_zynq::ram;
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use log::{debug, error, info};
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@@ -4,7 +4,10 @@ use cslice::CSlice;
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#[cfg(has_drtio)]
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use super::{KERNEL_CHANNEL_0TO1, KERNEL_CHANNEL_1TO0, Message};
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use crate::{artiq_raise, kernel::core1::{__rtio_page, L2_TEXT_TABLE}, pl::csr, rtio_core};
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use crate::{artiq_raise,
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kernel::core1::{__rtio_page, L2_TEXT_TABLE},
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pl::csr,
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rtio_core};
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pub const RTIO_O_STATUS_WAIT: u8 = 1;
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pub const RTIO_O_STATUS_UNDERFLOW: u8 = 2;
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