forked from M-Labs/ionpak-thermostat
ad7172: refactor and add xor support
This commit is contained in:
parent
0697914182
commit
f7af12adf5
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@ -30,6 +30,11 @@ dependencies = [
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"rustc_version 0.2.3 (registry+https://github.com/rust-lang/crates.io-index)",
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]
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[[package]]
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name = "bit_field"
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version = "0.10.0"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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[[package]]
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name = "bitflags"
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version = "1.1.0"
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@ -123,6 +128,8 @@ dependencies = [
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name = "ionpak-firmware"
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version = "1.0.0"
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dependencies = [
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"bit_field 0.10.0 (registry+https://github.com/rust-lang/crates.io-index)",
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"byteorder 1.3.2 (registry+https://github.com/rust-lang/crates.io-index)",
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"cortex-m 0.5.10 (registry+https://github.com/rust-lang/crates.io-index)",
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"cortex-m-rt 0.6.10 (registry+https://github.com/rust-lang/crates.io-index)",
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"cortex-m-semihosting 0.3.5 (registry+https://github.com/rust-lang/crates.io-index)",
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@ -320,6 +327,7 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
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"checksum aligned 0.3.1 (registry+https://github.com/rust-lang/crates.io-index)" = "d3a316c7ea8e1e9ece54862c992def5a7ac14de9f5832b69d71760680efeeefa"
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"checksum as-slice 0.1.0 (registry+https://github.com/rust-lang/crates.io-index)" = "293dac66b274fab06f95e7efb05ec439a6b70136081ea522d270bc351ae5bb27"
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"checksum bare-metal 0.2.5 (registry+https://github.com/rust-lang/crates.io-index)" = "5deb64efa5bd81e31fcd1938615a6d98c82eafcbcd787162b6f63b91d6bac5b3"
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"checksum bit_field 0.10.0 (registry+https://github.com/rust-lang/crates.io-index)" = "a165d606cf084741d4ac3a28fb6e9b1eb0bd31f6cd999098cfddb0b2ab381dc0"
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"checksum bitflags 1.1.0 (registry+https://github.com/rust-lang/crates.io-index)" = "3d155346769a6855b86399e9bc3814ab343cd3d62c7e985113d46a0ec3c281fd"
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"checksum build_const 0.2.1 (registry+https://github.com/rust-lang/crates.io-index)" = "39092a32794787acd8525ee150305ff051b0aa6cc2abaf193924f5ab05425f39"
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"checksum byteorder 1.3.2 (registry+https://github.com/rust-lang/crates.io-index)" = "a7c3dd8985a7111efc5c80b44e23ecdd8c007de8ade3b96595387e812b957cf5"
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@ -16,6 +16,8 @@ tm4c129x = { version = "0.8", features = ["rt"] }
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embedded-hal = { version = "0.2", features = ["unproven"] }
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nb = "0.1"
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cortex-m-semihosting = "0.3"
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byteorder = { version = "1.3", default-features = false }
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bit_field = "0.10"
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[dependencies.smoltcp]
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git = "https://github.com/m-labs/smoltcp"
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@ -1,37 +1,167 @@
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use embedded_hal::digital::v2::OutputPin;
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use embedded_hal::blocking::spi::Transfer;
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use byteorder::{BigEndian, ByteOrder};
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use bit_field::BitField;
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#[allow(unused)]
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#[derive(Clone, Copy)]
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trait Register {
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type Data: RegisterData;
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fn address(&self) -> u8;
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}
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trait RegisterData {
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fn empty() -> Self;
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fn as_mut(&mut self) -> &mut [u8];
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}
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macro_rules! def_reg {
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($Reg: ident, $reg: ident, $addr: expr, $size: expr) => (
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struct $Reg;
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impl Register for $Reg {
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type Data = $reg::Data;
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fn address(&self) -> u8 {
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$addr
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}
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}
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mod $reg {
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pub struct Data(pub [u8; $size]);
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impl super::RegisterData for Data {
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fn empty() -> Self {
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Data([0; $size])
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}
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fn as_mut(&mut self) -> &mut [u8] {
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&mut self.0
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}
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}
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}
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)
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}
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def_reg!(Status, status, 0x00, 1);
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impl status::Data {
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/// Is there new data to read?
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fn ready(&self) -> bool {
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! self.0[0].get_bit(7)
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}
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/// Channel for which data is ready
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fn channel(&self) -> u8 {
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self.0[0].get_bits(0..=1)
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}
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fn adc_error(&self) -> bool {
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self.0[0].get_bit(6)
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}
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fn crc_error(&self) -> bool {
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self.0[0].get_bit(5)
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}
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fn reg_error(&self) -> bool {
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self.0[0].get_bit(4)
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}
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}
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def_reg!(IfMode, if_mode, 0x02, 2);
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impl if_mode::Data {
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fn set_crc(&mut self, mode: ChecksumMode) {
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self.0[1].set_bits(2..=3, mode as u8);
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}
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}
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def_reg!(Data, data, 0x04, 3);
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impl data::Data {
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fn data(&self) -> u32 {
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(u32::from(self.0[0]) << 16) |
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(u32::from(self.0[1]) << 8) |
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u32::from(self.0[2])
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}
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}
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def_reg!(Id, id, 0x07, 2);
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impl id::Data {
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fn id(&self) -> u16 {
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BigEndian::read_u16(&self.0)
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}
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}
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// #[allow(unused)]
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// #[derive(Clone, Copy)]
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// #[repr(u8)]
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// pub enum Register {
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// Status = 0x00,
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// AdcMode = 0x01,
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// IfMode = 0x02,
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// RegCheck = 0x03,
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// Data = 0x04,
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// GpioCon = 0x06,
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// Id = 0x07,
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// Ch0 = 0x10,
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// Ch1 = 0x11,
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// Ch2 = 0x12,
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// Ch3 = 0x13,
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// SetupCon0 = 0x20,
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// SetupCon1 = 0x21,
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// SetupCon2 = 0x22,
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// SetupCon3 = 0x23,
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// FiltCon0 = 0x28,
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// FiltCon1 = 0x29,
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// FiltCon2 = 0x2A,
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// FiltCon3 = 0x2B,
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// Offset0 = 0x30,
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// Offset1 = 0x31,
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// Offset2 = 0x32,
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// Offset3 = 0x33,
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// Gain0 = 0x38,
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// Gain1 = 0x39,
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// Gain2 = 0x3A,
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// Gain3 = 0x3B,
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// }
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#[derive(Clone, Debug, PartialEq)]
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pub enum AdcError<SPI> {
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SPI(SPI),
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ChecksumMismatch(Option<u8>, Option<u8>),
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}
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impl<SPI> From<SPI> for AdcError<SPI> {
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fn from(e: SPI) -> Self {
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AdcError::SPI(e)
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}
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}
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#[derive(Clone, Copy, PartialEq)]
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#[repr(u8)]
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pub enum Register {
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Status = 0x00,
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AdcMode = 0x01,
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IfMode = 0x02,
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RegCheck = 0x03,
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Data = 0x04,
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GpioCon = 0x06,
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Id = 0x07,
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Ch0 = 0x10,
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Ch1 = 0x11,
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Ch2 = 0x12,
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Ch3 = 0x13,
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SetupCon0 = 0x20,
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SetupCon1 = 0x21,
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SetupCon2 = 0x22,
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SetupCon3 = 0x23,
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FiltCon0 = 0x28,
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FiltCon1 = 0x29,
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FiltCon2 = 0x2A,
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FiltCon3 = 0x2B,
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Offset0 = 0x30,
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Offset1 = 0x31,
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Offset2 = 0x32,
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Offset3 = 0x33,
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Gain0 = 0x38,
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Gain1 = 0x39,
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Gain2 = 0x3A,
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Gain3 = 0x3B,
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pub enum ChecksumMode {
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Off = 0b00,
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Xor = 0b01,
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/// Not implemented
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#[allow(unused)]
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Crc = 0b10,
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}
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struct Checksum {
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mode: ChecksumMode,
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state: u8,
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}
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impl Checksum {
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pub fn new(mode: ChecksumMode) -> Self {
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Checksum { mode, state: 0 }
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}
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pub fn feed(&mut self, input: u8) {
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match self.mode {
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ChecksumMode::Off => {},
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ChecksumMode::Xor => self.state ^= input,
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ChecksumMode::Crc => {
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// TODO
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}
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}
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}
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pub fn result(&self) -> Option<u8> {
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match self.mode {
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ChecksumMode::Off => None,
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_ => Some(self.state)
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}
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}
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}
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/// AD7172-2 implementation
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@ -40,79 +170,141 @@ pub enum Register {
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pub struct Adc<SPI: Transfer<u8>, NSS: OutputPin> {
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spi: SPI,
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nss: NSS,
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checksum_mode: ChecksumMode,
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}
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impl<SPI: Transfer<u8>, NSS: OutputPin> Adc<SPI, NSS> {
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pub fn new(spi: SPI, mut nss: NSS) -> Result<Self, SPI::Error> {
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let _ = nss.set_high();
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let mut adc = Adc { spi, nss};
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let mut adc = Adc {
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spi, nss,
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checksum_mode: ChecksumMode::Off,
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};
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adc.reset()?;
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let mut buf = [0, 0, 0];
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adc.write_reg(Register::AdcMode, &mut buf)?;
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let mut buf = [0, 1, 0];
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adc.write_reg(Register::IfMode, &mut buf)?;
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let mut buf = [0, 0, 0];
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adc.write_reg(Register::GpioCon, &mut buf)?;
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Ok(adc)
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}
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/// `0x00DX` for AD7271-2
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pub fn identify(&mut self) -> Option<u16> {
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let mut buf = [0u8; 3];
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self.read_reg(Register::Id, &mut buf)
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.ok()
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.map(|()| (u16::from(buf[1]) << 8) | u16::from(buf[2]))
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pub fn identify(&mut self) -> Result<u16, AdcError<SPI::Error>> {
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self.read_reg(&Id)
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.map(|id| id.id())
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}
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pub fn set_checksum_mode(&mut self, mode: ChecksumMode) -> Result<(), AdcError<SPI::Error>> {
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let mut ifmode = self.read_reg(&IfMode)?;
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ifmode.set_crc(mode);
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self.checksum_mode = mode;
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self.write_reg(&IfMode, &mut ifmode)?;
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Ok(())
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}
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// pub fn setup(&mut self) -> Result<(), SPI::Error> {
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// let mut buf = [0, 0, 0];
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// adc.write_reg(Register::AdcMode, &mut buf)?;
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// let mut buf = [0, 1, 0];
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// adc.write_reg(Register::IfMode, &mut buf)?;
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// let mut buf = [0, 0, 0];
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// adc.write_reg(Register::GpioCon, &mut buf)?;
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// Ok(())
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// }
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/// Returns the channel the data is from
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pub fn data_ready(&mut self) -> Option<u8> {
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let mut buf = [0u8; 2];
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self.read_reg(Register::Status, &mut buf)
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.ok()
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.and_then(|()| {
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if buf[1] & 0x80 == 0 {
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None
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pub fn data_ready(&mut self) -> Result<Option<u8>, AdcError<SPI::Error>> {
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self.read_reg(&Status)
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.map(|status| {
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if status.ready() {
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Some(status.channel())
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} else {
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Some(buf[1] & 0x3)
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None
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}
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})
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}
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/// Get data
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pub fn read_data(&mut self) -> Result<u32, SPI::Error> {
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let mut buf = [0u8; 4];
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self.read_reg(Register::Data, &mut buf)?;
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let result =
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(u32::from(buf[1]) << 16) |
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(u32::from(buf[2]) << 8) |
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u32::from(buf[3]);
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pub fn read_data(&mut self) -> Result<u32, AdcError<SPI::Error>> {
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self.read_reg(&Data)
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.map(|data| data.data())
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}
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fn read_reg<R: Register>(&mut self, reg: &R) -> Result<R::Data, AdcError<SPI::Error>> {
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let mut reg_data = R::Data::empty();
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let address = 0x40 | reg.address();
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let mut checksum = Checksum::new(self.checksum_mode);
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checksum.feed(address);
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let checksum_out = checksum.result();
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let checksum_in = self.transfer(address, reg_data.as_mut(), checksum_out)?;
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for &mut b in reg_data.as_mut() {
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checksum.feed(b);
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}
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let checksum_expected = checksum.result();
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if checksum_expected != checksum_in {
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return Err(AdcError::ChecksumMismatch(checksum_expected, checksum_in));
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}
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Ok(reg_data)
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}
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fn write_reg<R: Register>(&mut self, reg: &R, reg_data: &mut R::Data) -> Result<(), AdcError<SPI::Error>> {
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let address = reg.address();
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let checksum_out = match self.checksum_mode {
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ChecksumMode::Off => None,
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ChecksumMode::Xor => {
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let mut xor = address;
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for b in reg_data.as_mut() {
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xor ^= *b;
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}
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Some(xor)
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}
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ChecksumMode::Crc => panic!("Not implemented"),
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};
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self.transfer(address, reg_data.as_mut(), checksum_out)?;
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Ok(())
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}
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fn update_reg<R, F, A>(&mut self, reg: &R, f: F) -> Result<A, AdcError<SPI::Error>>
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where
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R: Register,
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F: FnOnce(&mut R::Data) -> A,
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{
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let mut reg_data = self.read_reg(reg)?;
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let result = f(&mut reg_data);
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self.write_reg(reg, &mut reg_data)?;
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Ok(result)
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}
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fn read_reg(&mut self, reg: Register, buffer: &'_ mut [u8]) -> Result<(), SPI::Error> {
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buffer[0] = 0x40 | (reg as u8);
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self.transfer(buffer)?;
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Ok(())
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}
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fn write_reg(&mut self, reg: Register, buffer: &'_ mut [u8]) -> Result<(), SPI::Error> {
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buffer[0] = reg as u8;
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self.transfer(buffer)?;
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Ok(())
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}
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pub fn reset(&mut self) -> Result<(), SPI::Error> {
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let mut buf = [0xFFu8; 8];
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self.transfer(&mut buf)?;
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let _ = self.nss.set_low();
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let result = self.spi.transfer(&mut buf);
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let _ = self.nss.set_high();
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result?;
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Ok(())
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}
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fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], SPI::Error> {
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fn transfer<'w>(&mut self, addr: u8, reg_data: &'w mut [u8], checksum: Option<u8>) -> Result<Option<u8>, SPI::Error> {
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let mut addr_buf = [addr];
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let _ = self.nss.set_low();
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let result = self.spi.transfer(words);
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let result = match self.spi.transfer(&mut addr_buf) {
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Ok(_) => self.spi.transfer(reg_data),
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Err(e) => Err(e),
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};
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let result = match (result, checksum) {
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(Ok(_),None) =>
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Ok(None),
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(Ok(_), Some(checksum_out)) => {
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let mut checksum_buf = [checksum_out; 1];
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match self.spi.transfer(&mut checksum_buf) {
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Ok(_) => Ok(Some(checksum_buf[0])),
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Err(e) => Err(e),
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}
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}
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(Err(e), _) =>
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Err(e),
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};
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let _ = self.nss.set_high();
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result
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}
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}
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@ -106,13 +106,28 @@ fn main() -> ! {
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loop {
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let r = adc.identify();
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match r {
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None =>
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writeln!(stdout, "Cannot identify ADC!").unwrap(),
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Some(id) if id & 0xFFF0 == 0x00D0 => {
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Err(e) =>
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writeln!(stdout, "Cannot identify ADC: {:?}", e).unwrap(),
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Ok(id) if id & 0xFFF0 == 0x00D0 => {
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writeln!(stdout, "ADC id: {:04X}", id).unwrap();
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break;
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}
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Some(id) =>
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Ok(id) =>
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writeln!(stdout, "Corrupt ADC id: {:04X}", id).unwrap(),
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};
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}
|
||||
writeln!(stdout, "AD7172: setting checksum mode to XOR").unwrap();
|
||||
adc.set_checksum_mode(ad7172::ChecksumMode::Xor).unwrap();
|
||||
loop {
|
||||
let r = adc.identify();
|
||||
match r {
|
||||
Err(e) =>
|
||||
writeln!(stdout, "Cannot identify ADC: {:?}", e).unwrap(),
|
||||
Ok(id) if id & 0xFFF0 == 0x00D0 => {
|
||||
writeln!(stdout, "ADC id: {:04X}", id).unwrap();
|
||||
break;
|
||||
}
|
||||
Ok(id) =>
|
||||
writeln!(stdout, "Corrupt ADC id: {:04X}", id).unwrap(),
|
||||
};
|
||||
}
|
||||
|
@ -165,21 +180,27 @@ fn main() -> ! {
|
|||
];
|
||||
|
||||
let mut time = 0i64;
|
||||
let mut data = 0;
|
||||
let mut data = None;
|
||||
// if a socket has sent the latest data
|
||||
let mut socket_pending = [false; 8];
|
||||
loop {
|
||||
adc.data_ready()
|
||||
.map(|channel| {
|
||||
adc.read_data()
|
||||
.map(|new_data| {
|
||||
writeln!(stdout, "adc data: {:?}", new_data).unwrap();
|
||||
data = new_data;
|
||||
if channel == 0 {
|
||||
for p in socket_pending.iter_mut() {
|
||||
*p = true;
|
||||
}
|
||||
.and_then(|channel|
|
||||
channel.map(|channel|
|
||||
adc.read_data().map(|new_data| {
|
||||
data = Some(Ok((channel, new_data)));
|
||||
for p in socket_pending.iter_mut() {
|
||||
*p = true;
|
||||
}
|
||||
})
|
||||
).unwrap_or(Ok(()))
|
||||
)
|
||||
.map_err(|e| {
|
||||
data = Some(Err(e));
|
||||
for p in socket_pending.iter_mut() {
|
||||
*p = true;
|
||||
}
|
||||
|
||||
});
|
||||
for (&tcp_handle, pending) in handles.iter().zip(socket_pending.iter_mut()) {
|
||||
let socket = &mut *sockets.get::<TcpSocket>(tcp_handle);
|
||||
|
@ -188,7 +209,18 @@ fn main() -> ! {
|
|||
}
|
||||
|
||||
if socket.may_send() && *pending {
|
||||
let _ = writeln!(socket, "{}\r", data);
|
||||
match &data {
|
||||
Some(Ok((channel, input))) => {
|
||||
let _ = writeln!(socket, "channel={} input={}\r", channel, input);
|
||||
}
|
||||
Some(Err(ad7172::AdcError::ChecksumMismatch(Some(expected), Some(input)))) => {
|
||||
let _ = writeln!(socket, "checksum_expected={:02X} checksum_input={:02X}\r", expected, input);
|
||||
}
|
||||
Some(Err(e)) => {
|
||||
let _ = writeln!(socket, "adc_error={:?}\r", e);
|
||||
}
|
||||
None => {}
|
||||
}
|
||||
*pending = false;
|
||||
}
|
||||
}
|
||||
|
|
Loading…
Reference in New Issue