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Raise ADC clock to 32 MHz (maximum).

This commit is contained in:
whitequark 2017-05-08 13:28:25 +00:00
parent 592aee4735
commit b07cd31572
1 changed files with 2 additions and 1 deletions
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3
firmware/src/main.rs
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@ -237,7 +237,8 @@ fn main() {
let adc0 = tm4c129x::ADC0.borrow(cs); let adc0 = tm4c129x::ADC0.borrow(cs);
// Due to silicon erratum, this HAS to use PLL. PIOSC is not a suitable source. // Due to silicon erratum, this HAS to use PLL. PIOSC is not a suitable source.
adc0.cc.write(|w| w.cs().syspll().clkdiv().bits(16)); // fADC=32 MHz
adc0.cc.write(|w| w.cs().syspll().clkdiv().bits(10));
adc0.im.write(|w| w.mask0().bit(true)); adc0.im.write(|w| w.mask0().bit(true));
adc0.emux.write(|w| w.em0().timer()); adc0.emux.write(|w| w.em0().timer());
adc0.ssmux0.write(|w| { adc0.ssmux0.write(|w| {