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ad7172: setup adc

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This commit is contained in:
Astro 2019-09-17 00:13:46 +02:00
parent 7e51585aa9
commit 4587406d44
4 changed files with 28 additions and 1 deletions
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19
firmware/src/ad7172/adc.rs
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@ -2,7 +2,10 @@ use embedded_hal::digital::v2::OutputPin;
use embedded_hal::blocking::spi::Transfer; use embedded_hal::blocking::spi::Transfer;
use super::checksum::{ChecksumMode, Checksum}; use super::checksum::{ChecksumMode, Checksum};
use super::AdcError; use super::AdcError;
use super::{regs, regs::RegisterData, Input}; use super::{
regs, regs::RegisterData,
Input, RefSource, PostFilter, DigitalFilterOrder,
};
/// AD7172-2 implementation /// AD7172-2 implementation
/// ///
@ -41,13 +44,27 @@ impl<SPI: Transfer<u8>, NSS: OutputPin> Adc<SPI, NSS> {
Ok(()) Ok(())
} }
pub fn set_sync_enable(&mut self, enable: bool) -> Result<(), AdcError<SPI::Error>> {
self.update_reg(&regs::GpioCon, |data| {
data.set_sync_en(enable);
})
}
pub fn setup_channel( pub fn setup_channel(
&mut self, index: u8, in_pos: Input, in_neg: Input &mut self, index: u8, in_pos: Input, in_neg: Input
) -> Result<(), AdcError<SPI::Error>> { ) -> Result<(), AdcError<SPI::Error>> {
self.update_reg(&regs::SetupCon { index }, |data| { self.update_reg(&regs::SetupCon { index }, |data| {
data.set_bipolar(false); data.set_bipolar(false);
data.set_refbuf_pos(true);
data.set_refbuf_neg(true);
data.set_ainbuf_pos(true);
data.set_ainbuf_neg(true);
data.set_ref_sel(RefSource::External);
})?; })?;
self.update_reg(&regs::FiltCon { index }, |data| { self.update_reg(&regs::FiltCon { index }, |data| {
data.set_enh_filt_en(true);
data.set_enh_filt(PostFilter::F16SPS);
data.set_order(DigitalFilterOrder::Sinc5Sinc1);
// 10 Hz data rate // 10 Hz data rate
data.set_odr(0b10011); data.set_odr(0b10011);
})?; })?;

4
firmware/src/ad7172/mod.rs
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@ -113,9 +113,13 @@ impl fmt::Display for RefSource {
#[repr(u8)] #[repr(u8)]
pub enum PostFilter { pub enum PostFilter {
/// 27 SPS, 47 dB rejection, 36.7 ms settling
F27SPS = 0b010, F27SPS = 0b010,
/// 21.25 SPS, 62 dB rejection, 40 ms settling
F21SPS = 0b011, F21SPS = 0b011,
/// 20 SPS, 86 dB rejection, 50 ms settling
F20SPS = 0b101, F20SPS = 0b101,
/// 16.67 SPS, 92 dB rejection, 60 ms settling
F16SPS = 0b110, F16SPS = 0b110,
Invalid = 0b111, Invalid = 0b111,
} }

5
firmware/src/ad7172/regs.rs
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@ -152,6 +152,11 @@ impl data::Data {
} }
} }
def_reg!(GpioCon, gpio_con, 0x06, 2);
impl gpio_con::Data {
reg_bit!(sync_en, set_sync_en, 0, 3, "Enables the SYNC/ERROR pin as a sync input");
}
def_reg!(Id, id, 0x07, 2); def_reg!(Id, id, 0x07, 2);
impl id::Data { impl id::Data {
pub fn id(&self) -> u16 { pub fn id(&self) -> u16 {

1
firmware/src/main.rs
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@ -148,6 +148,7 @@ fn main() -> ! {
writeln!(stdout, "Corrupt ADC id: {:04X}", id).unwrap(), writeln!(stdout, "Corrupt ADC id: {:04X}", id).unwrap(),
}; };
} }
adc.set_sync_enable(false).unwrap();
// SENS0_{P,N} // SENS0_{P,N}
adc.setup_channel(0, ad7172::Input::Ain0, ad7172::Input::Ain1).unwrap(); adc.setup_channel(0, ad7172::Input::Ain0, ad7172::Input::Ain1).unwrap();
// SENS1_{P,N} // SENS1_{P,N}